Samsung patents method for creating finer patterns in semiconductor chips
Samsung describes a manufacturing technique for creating very small patterns on semiconductor wafers. The process uses temporary structures called spacers to define the final shape of the circuit lines before removing the initial guides.
In the filing’s own words
A method of manufacturing a semiconductor device includes forming a plurality of reference patterns and a peripheral pattern on a feature layer by using a first material such that the peripheral pattern is connected to end portions of the plurality of reference patterns; forming a plurality of first spacers on both sidewalls of each of the plurality of reference patterns by using a second material; removing the plurality of reference patterns; forming a plurality of second spacers on both sidewalls of each of the plurality of first spacers by using the first material; removing the plurality of first spacers so that the plurality of second spacers and the peripheral pattern remain on the feature layer; and patterning the feature layer by using the plurality of second spacers and the peripheral pattern as an etch mask.
What exactly they claim (claim 1)
1. A method of manufacturing a semiconductor device, the method comprising: forming a plurality of reference patterns and a peripheral pattern on a feature layer using a first material such that the peripheral pattern is connected to end portions of the plurality of reference patterns; forming a plurality of first spacers on opposite sidewalls of each of the plurality of reference patterns using a second material; removing the plurality of reference patterns; forming a plurality of second spacers on opposite sidewalls of each of the plurality of first spacers using the first material, wherein the feature layer is exposed between neighboring pairs of first spacers of the plurality of first spacers; forming a gap-fill insulation layer to cover the feature layer, the plurality of first spacers, and the plurality of second spacers, the gap-fill insulation layer contacting the feature layer; removing the plurality of first spacers and the gap-fill insulation layer so that the plurality of second spacers and the peripheral pattern remain on the feature layer with the feature layer exposed between neighboring pairs of second spacers of the plurality of second spacers; and patterning the feature layer using the plurality of second spacers and the peripheral pattern as an etch mask.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Method of fine pitch pattering for semiconductor device and method of manufacturing the same
- Patent number
- US12740358B2
- Application number
- 18102897
- Filed
- Jan 30, 2023
- Granted
- Sep 15, 2026
- Inventors
- 5
- Claims
- 18
Classified under
H10P 50/695 Electricity & electronicsH10B 12/09 Electricity & electronicsH10P 50/71 Electricity & electronicsH10P 50/73 Electricity & electronicsH10P 76/405 Electricity & electronicsH10P 76/408 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.