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SamsungGranted patentChips & hardwareInterest 3/10

Samsung patents memory layout that uses a raised insulating layer

This filing describes a specific arrangement for memory chips where a word line and bit line cross to form a storage cell. It places a filling pattern on the side of the cell and adds an insulating layer between that filler and the bit line. The key feature is that the bottom of this insulating layer sits higher than the bottom of the cell's upper electrode.

Why it mattersThis is a detailed manufacturing technique that may help engineers build memory components with more precise spacing and protection.

In the filing’s own words

A semiconductor device includes a word line extending in a first direction. A bit line extends on the word line in a second direction intersecting the first direction. A memory cell is disposed between the word line and the bit line. The memory cell includes a lower electrode, a selection element, and an upper electrode sequentially disposed on the word line. A filling pattern is on a side surface of the memory cell. An etch stop pattern includes an insulating material between the filling pattern and the bit line. A lower surface of the etch stop pattern is positioned at a higher level than a level of a lower surface of the upper electrode.

What exactly they claim (claim 1)

1. A semiconductor device comprising: a word line extending in a first direction; a bit line extending on the word line in a second direction intersecting the first direction; a memory cell disposed between the word line and the bit line, the memory cell including a lower electrode, a selection element, and an upper electrode sequentially disposed on the word line; a filling pattern on a side surface of the memory cell; and an etch stop pattern including an insulating material between the filling pattern and the bit line, wherein a lower surface of the etch stop pattern is positioned at a higher level than a level of a lower surface of the upper electrode.

Facts

Company
Samsung (SAMSUNG ELECTRONICS CO., LTD.)
Official title
Semiconductor device and method of manufacturing the same
Patent number
US12740340B2
Application number
18753280
Filed
Jun 25, 2024
Granted
Sep 15, 2026
Inventors
2
Claims
20

Classified under

H10N 70/841 Electricity & electronicsH10B 63/24 Electricity & electronicsH10B 63/84 Electricity & electronicsH10N 70/063 Electricity & electronicsH10N 70/8828 Electricity & electronics

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.