Samsung patents 3D chip design with stacked layers and uneven wiring
This patent describes a method for building a 3D semiconductor device by stacking upper and lower layers of channels and source/drain patterns. It features a specific 'wide via' connection that links the upper and lower layers, with one part of the connection sitting lower than the other to manage electrical flow.
In the filing’s own words
A three-dimensional semiconductor device may include a back-side metal layer, a lower channel pattern on the back-side metal layer, first and second lower source/drain patterns, which are spaced apart from each other in a first direction with the lower channel pattern interposed therebetween, the first lower source/drain pattern being connected to the lower channel pattern, an upper channel pattern on the lower channel pattern, a first upper source/drain pattern on the first lower source/drain pattern, the first upper source/drain pattern being connected to the upper channel pattern, a second upper source/drain pattern on the second lower source/drain pattern, and a wide via electrically connecting the first upper source/drain pattern to the second lower source/drain pattern. The wide via may include first and second via portions having first and second top surfaces, and here, the second top surface may be located at a level lower than the first top surface.
What exactly they claim (claim 1)
1. A three-dimensional (3D) semiconductor device, comprising: a back-side metal layer; a lower channel pattern on the back-side metal layer; a first lower source/drain pattern and a second lower source/drain pattern spaced apart from each other in a first direction with the lower channel pattern interposed therebetween, the first lower source/drain pattern connected to the lower channel pattern; an upper channel pattern on the lower channel pattern; a first upper source/drain pattern on the first lower source/drain pattern, the first upper source/drain pattern connected to the upper channel pattern; a second upper source/drain pattern on the second lower source/drain pattern; and a wide via electrically connecting the first upper source/drain pattern to the second lower source/drain pattern, wherein the wide via comprises a first via portion having a first top surface and a second via portion having a second top surface at a level lower than the first top surface.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Three-dimensional semiconductor device and method of fabricating the same
- Patent number
- US12740139B2
- Application number
- 18435305
- Filed
- Feb 7, 2024
- Granted
- Sep 15, 2026
- Inventors
- 5
- Claims
- 20
Classified under
H10D 84/856 Electricity & electronicsH10D 30/014 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6729 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 62/121 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.