Samsung patents chip-making step to cut gate lines with less damage

1. A method of manufacturing a semiconductor device, comprising: providing a semiconductor structure including a plurality of active patterns that extend on a substrate in a first direction, a plurality of gate lines that intersect the plurality of active patterns and extend in a second direction that intersects the first direction, and an interlayer insulating layer having a plurality of intergate insulating portions that overlap in a direction perpendicular to a surface of the substrate respective ones of the plurality of active patterns and are respectively between ones of the plurality of gate lines, wherein each of the plurality of gate lines includes a gate electrode and a gate capping layer on the gate electrode; forming a mask layer on the plurality of gate lines and the plurality of intergate insulating portions; forming an opening that exposes a cut region of the plurality of gate lines in the mask layer; forming a separation hole by removing a portion of the gate capping layer exposed by the opening, using the mask layer; forming a pyrolysis material pattern in the separation hole, wherein an upper surface of the pyrolysis material pattern is closer to the substrate than an upper surface of the mask layer; exposing a side wall portion of the separation hole by decomposing a portion of the pyrolysis material pattern; forming an etch stop layer on the upper surface of the mask layer and on the exposed side wall portion of the separation hole, wherein exposing the side wall portion of the separation hole by decomposing the portion of the pyrolysis material pattern comprises removing a source material of the etch stop layer adsorbed on the pyrolysis material pattern while decomposing the portion of the pyrolysis material pattern; and selectively removing a portion of the gate electrode exposed by the separation hole using the etch stop layer.