Samsung patents chip design using controlled defects in source/drain areas
Samsung describes a semiconductor structure where the source and drain regions of a transistor contain specific crystal defects called stacking faults. The filing details how these faults are positioned vertically within the material to avoid the lower sheet patterns of the active region.
In the filing’s own words
A semiconductor device includes an active pattern having a lower pattern, and a plurality of sheet patterns spaced apart from the lower pattern in a first direction; first and second structures disposed on the lower pattern, wherein the first and second structures are arranged and spaced apart from each other in a second direction; a source/drain recess defined between first and second gate structures; and a source/drain pattern filling the source/drain recess, wherein the source/drain pattern includes a stacking fault spaced apart from the lower pattern.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: an active pattern including a lower pattern and sheet patterns, the sheet patterns being spaced apart from the lower pattern in a first direction which is a vertical direction; first and second gate structures on the lower pattern, the first and second gate structures being spaced apart from each other in a second direction which is a horizontal direction; a source/drain recess between the first and second gate structures, the source/drain recess extending vertically from a first height below a lowermost sheet pattern of the sheet patterns to a second height above an uppermost sheet pattern of the sheet patterns, the lowermost sheet pattern having no additional sheet patterns of the active pattern therebelow; and a source/drain pattern filling the source/drain recess from the first height to the second height, the source/drain pattern including at least one stacking fault spaced apart from the lower pattern, and not including any stacking faults at a height below a height of the lowermost sheet pattern from a bottom surface of the active pattern, wherein the at least one stacking fault extends from a first point overlapping a sidewall of one of the sheet patterns in the second direction toward a top surface of the source/drain pattern or extends from the first point toward a bottom surface of the source/drain recess.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Semiconductor device including source/drain pattern having stacking fault
- Patent number
- US12740127B2
- Application number
- 18138877
- Filed
- Apr 25, 2023
- Granted
- Sep 15, 2026
- Inventors
- 5
- Claims
- 20
Classified under
H10D 64/258 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 30/6757 Electricity & electronicsH10D 62/121 Electricity & electronicsH10D 64/017 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.