Samsung patents chip contact with stacked metal layers
Samsung has been granted a patent for a semiconductor device design that improves how electrical connections are made to chips. The invention uses a contact made of three stacked layers of the same metal, where each layer has a different internal crystal structure to create specific boundaries between them.
In the filing’s own words
A semiconductor device may include a substrate, an active pattern extending in a first horizontal direction on the substrate, a gate electrode extending in a second horizontal direction different from the first horizontal direction on the active pattern, a source/drain region on at least a first side of the gate electrode on the active pattern, and a source/drain contact connected to the source/drain region on the first side of the gate electrode. The source/drain contact may include first, second, and third layers which are sequentially stacked, the first to third layers including the same metal, with each layer having a respective crystal orientation. The source/drain contact may include a first grain boundary at an interface between the first layer and the second layer, and a second grain boundary at an interface between the second layer and the third layer.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a substrate; an active pattern that extends in a first horizontal direction on the substrate; a gate electrode that extends in a second horizontal direction that is different from the first horizontal direction on the active pattern; a source/drain region on at least a first side of the gate electrode on the active pattern; and a source/drain contact connected to the source/drain region on the first side of the gate electrode, the source/drain contact including first, second, and third layers which are sequentially stacked, the first, second, and third layers of the source/drain contact including a same metal, the first layer of the source/drain contact having a first crystal orientation, the second layer of the source/drain contact having a second crystal orientation different from the first crystal orientation, and the third layer of the source/drain contact having a third crystal orientation different from the second crystal orientation, wherein the source/drain contact includes a first grain boundary at an interface between the first layer and the second layer of the source/drain contact, and a second grain boundary at an interface between the second layer and the third layer of the source/drain contact.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Semiconductor devices
- Patent number
- US12740111B2
- Application number
- 18624253
- Filed
- Apr 2, 2024
- Granted
- Sep 15, 2026
- Inventors
- 5
- Claims
- 20
Classified under
H10D 62/121 Electricity & electronicsH10D 30/014 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 30/6757 Electricity & electronicsH10D 64/017 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.