Samsung patents chip design using buried lines for better memory
Samsung describes an integrated circuit layout that separates memory cells from control circuits. It uses narrow trenches in the chip's base, lined with insulating material and filled with conductive lines, to create specific electrical contacts.
In the filing’s own words
An integrated circuit device includes a substrate including a cell array region and a peripheral circuit region, a first ion implantation region located in an upper portion of the substrate in the peripheral circuit region, the first ion implantation region having a plurality of line trenches that extend in a first horizontal direction and cross the first ion implantation region, a plurality of lower capacitor dielectric films with each lower capacitor dielectric film configured to respectively cover inner walls of a respective line trench, a plurality of buried conductive lines that each partially fill a respective line trench and that are each respectively disposed on a respective lower capacitor dielectric film, a plurality of first lower capacitor contacts that are each in contact with a respective buried conductive line, and a plurality of second lower capacitor contacts that are in contact with the first ion implantation region.
What exactly they claim (claim 1)
1. An integrated circuit device comprising: a substrate comprising a cell array region and a peripheral circuit region; a first ion implantation region located in an upper portion of the substrate in the peripheral circuit region, the first ion implantation region having a plurality of line trenches that extend in a first horizontal direction and cross the first ion implantation region; a plurality of lower capacitor dielectric films with each lower capacitor dielectric film configured to respectively cover inner walls of a respective line trench of the plurality of line trenches; a plurality of buried conductive lines that each partially fill a respective line trench of the plurality of line trenches and that are each respectively disposed on a respective lower capacitor dielectric film of the plurality of lower capacitor dielectric films; a plurality of first lower capacitor contacts that are each respectively in contact with a respective buried conductive line of the plurality of buried conductive lines; and a plurality of second lower capacitor contacts that are in contact with the first ion implantation region.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Integrated circuit device
- Patent number
- US12740077B2
- Application number
- 18598552
- Filed
- Mar 7, 2024
- Granted
- Sep 15, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10D 1/716 Electricity & electronicsH10B 12/30 Electricity & electronicsH10B 12/50 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.