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Samsung patents memory chip design with uneven transistor sizes

Samsung has been granted a patent for a semiconductor memory device that uses two different sizes of selection transistors at opposite ends of its conductive lines. The design specifies that one set of transistors has a wider gate than the other, with both positioned below the parallel lines on the substrate.

Why it mattersThis is a routine hardware optimization that likely improves the efficiency or performance of memory chips, but it does not describe a new consumer feature.

In the filing’s own words

A semiconductor memory device includes: first conductive lines provided on a substrate and extending in a first direction in parallel, each of the first conductive lines including a first end portion and a second end portion that are opposite to each other, the first direction being parallel to a top surface of the substrate; first selection transistors respectively connected to the first end portions of the first conductive lines; and second selection transistors respectively connected to the second end portions of the first conductive lines. Each of the first selection transistors may have a first gate width. Each of the second selection transistors may have a second gate width smaller than the first gate width.

What exactly they claim (claim 1)

1. A semiconductor memory device, comprising: first conductive lines provided on a substrate and extending in a first direction in parallel, the first direction being parallel to a top surface of the substrate; and first selection transistors and second selection transistors respectively connected to the first conductive lines, wherein: each of the first selection transistors has a first gate width, and each of the second selection transistors has a second gate width that is different from the first gate width, wherein the first selection transistors and the second selection transistors are located below the first conductive lines.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
Semiconductor memory device
Patent number
US12740070B2
Application number
18665005
Filed
May 15, 2024
Granted
Sep 15, 2026
Inventors
1
Claims
20

Classified under

H10B 63/30 Electricity & electronicsH10D 30/6211 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 30/6757 Electricity & electronicsH10D 62/118 Electricity & electronics

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.