Samsung patents chip design with offset wiring to improve memory connections
This patent describes a layout for semiconductor memory where electrical connections between layers are shifted slightly from the storage cells below. The design uses a barrier layer to cover the top of the storage electrodes before connecting them to the upper wiring.
In the filing’s own words
A semiconductor device includes a plurality of data storage patterns on a substrate, the plurality of data storage patterns spaced apart from each other in a first direction parallel to an upper surface of the substrate, a first upper conductive line on the plurality of data storage patterns, extending in the first direction and connected to the plurality of data storage patterns, a second upper conductive line on the first upper conductive line and extending in the first direction and a plurality of via contacts between the first upper conductive line and the second upper conductive line and spaced apart from each other in the first direction. The plurality of via contacts are arranged to be offset from the plurality of data storage patterns in the first direction.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a plurality of data storage patterns on a substrate, the plurality of data storage patterns spaced apart from each other in a first direction parallel to an upper surface of the substrate; a first upper conductive line on and above the plurality of data storage patterns, the first upper conductive line extending in the first direction and connected to the plurality of data storage patterns; a second upper conductive line on and above the first upper conductive line and extending in the first direction; and a plurality of via contacts between the first upper conductive line and the second upper conductive line and spaced apart from each other in the first direction, wherein the second upper conductive line is connected to the first upper conductive line through the plurality of via contacts, the plurality of via contacts are offset from the plurality of data storage patterns in the first direction between the first upper conductive line and the second upper conductive line, each of the plurality of data storage patterns includes an upper electrode, and the first upper conductive line includes a barrier pattern on upper surfaces of and on side surfaces of the upper electrodes of the plurality of data storage patterns.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Semiconductor device
- Patent number
- US12740069B2
- Application number
- 18473660
- Filed
- Sep 25, 2023
- Granted
- Sep 15, 2026
- Inventors
- 5
- Claims
- 20
Classified under
H10B 61/22 Electricity & electronicsH10W 20/42 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.