Samsung patents memory chip design with uneven support layers

1. A semiconductor memory device comprising: a first stacked structure including first gate electrodes sequentially stacked on a substrate; a first supporter layer disposed on the first stacked structure and divided by first cut patterns extending in a first direction, wherein each of the first cut patterns comprises first sub-cut patterns spaced apart from each other in a second direction intersecting the first direction; a second stacked structure including second gate electrodes sequentially stacked on the first supporter layer; a second supporter layer disposed on the second stacked structure and divided by second cut patterns extending in the first direction, wherein each of the second cut patterns comprises second sub-cut patterns spaced apart from each other in the second direction; a third stacked structure including third gate electrodes sequentially stacked on the second supporter layer; a third supporter layer disposed on the third stacked structure and divided by third cut patterns extending in the first direction, wherein each of the third cut patterns comprises third sub-cut patterns spaced apart from each other in the second direction; and a channel structure penetrating the first stacked structure, the first supporter layer, the second stacked structure, the second supporter layer and the third stacked structure, wherein the first supporter layer includes a first ratio of an area of the first cut patterns to an area of the first supporter layer, the second supporter layer includes a second ratio of an area of the second cut patterns to an area of the second supporter layer, the third supporter layer includes a third ratio of an area of the third cut patterns to an area of the third supporter layer, and at least one of the first ratio, the second ratio, or the third ratio is different from an other ratio of the first ratio, the second ratio, or the third ratio.