Samsung patents stacked memory design with new contact supports
Samsung describes a nonvolatile memory chip where gate electrodes are stacked in a stepped pattern to save space. The design uses specific support structures and insulating barriers to connect electrical contacts to the stacked layers without them touching.
In the filing’s own words
A nonvolatile memory device includes a substrate including a memory cell region and a connection region; a mold structure including a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked; a channel structure passing through the mold structure in the memory cell region; a first cell contact passing through the mold structure in the connection region, connected to a first gate electrode and electrically disconnected from a second gate electrode; a plurality of support structures surrounding the first cell contact planarly in the connection region and extending through the mold structure; and a dam structure located between the first cell contact and the second gate electrode in the connection region and apart from the first cell contact with an insulating ring therebetween.
What exactly they claim (claim 1)
1. A nonvolatile memory device comprising: a substrate including a memory cell region and a connection region; a mold structure including a plurality of gate electrodes sequentially stacked in the memory cell region and stacked stepwise in the connection region, and a plurality of mold insulating layers alternately stacked with the plurality of gate electrodes; a channel structure passing through the mold structure in the memory cell region and through the plurality of gate electrodes; a first cell contact passing through the mold structure in the connection region, connected to a first gate electrode among the plurality of gate electrodes and electrically disconnected from a second gate electrode among the plurality of gate electrodes; a plurality of support structures surrounding the first cell contact planarly in the connection region and respectively in a plurality of first holes passing through the mold structure; and a dam structure between the first cell contact and the second gate electrode in the connection region and apart from the first cell contact with an insulating ring therebetween, wherein the dam structure is in a plurality of second holes each having a diameter larger than a diameter of each of the plurality of first holes, and the plurality of first holes respectively pass through the plurality of second holes.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Nonvolatile memory device and electronic system including the same
- Patent number
- US12740062B2
- Application number
- 18581174
- Filed
- Feb 19, 2024
- Granted
- Sep 15, 2026
- Inventors
- 7
- Claims
- 20
Classified under
H10B 43/27 Electricity & electronicsH10B 41/27 Electricity & electronicsH10B 41/41 Electricity & electronicsH10B 43/40 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.