Samsung patents memory chip design with deeper trenches for better isolation
Samsung has secured a patent for a semiconductor memory device that uses trenches of different depths to separate active areas from inactive zones. The design places a material with a lower dielectric constant in the deeper sections of the isolation layer to manage electrical properties more effectively.
In the filing’s own words
A semiconductor memory device is provided. The semiconductor device may include a semiconductor substrate having a device isolation trench defining active regions, a device isolation layer disposed in the device isolation trench, gate trenches extending in a first direction and crossing the active regions of the semiconductor substrate and the device isolation layer, word lines disposed in the gate trenches, respectively, each of the gate trenches may include first trench sections in the active regions and second trench sections in the device isolation layer, the first trench sections may have a first depth, and the second trench section may have a second depth greater than the first depth, the device isolation layer may include a lower portion positioned at a level lower than bottom surfaces of the first trench sections and an upper portion on the lower portion, and the lower portion may be formed of a dielectric material having a lower dielectric constant than that of the upper portion.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a semiconductor substrate having a device isolation trench defining active regions; a device isolation layer disposed in the device isolation trench; gate trenches extending in a first direction with each gate trench crossing a respective plurality of the active regions of the semiconductor substrate and the device isolation layer; and word lines disposed in the gate trenches, respectively, wherein each of the gate trenches includes first trench sections in respective active regions and a second trench section in the device isolation layer, the first trench sections have a first depth, and the second trench section has a second depth greater than the first depth, wherein the device isolation layer includes a lower portion positioned at a level lower than bottom surfaces of the first trench sections and an upper portion on the lower portion, wherein the lower portion of the device isolation layer is formed of a dielectric material having a lower dielectric constant than that of the upper portion, and wherein an upper surface of the dielectric material having a lower dielectric constant than that of the upper portion is positioned at a level between the bottom surfaces of the first trench sections and a bottom surface of the second trench section.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Semiconductor memory device
- Patent number
- US12740049B2
- Application number
- 18383201
- Filed
- Oct 24, 2023
- Granted
- Sep 15, 2026
- Inventors
- 7
- Claims
- 18
Classified under
H10B 12/34 Electricity & electronicsH10B 12/053 Electricity & electronicsH10B 12/315 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.