Samsung patents memory chip design with buried gate structure

1. A semiconductor device, comprising: a substrate including an active region; a gate structure crossing the active region, the gate structure including: a gate pattern penetrating an upper portion of the active region in a first direction perpendicular to a bottom surface of the substrate, a metal-containing pattern on the gate pattern disposed at a first height above the bottom surface of the substrate and disposed so that in the first direction, the gate pattern is between the active region of the substrate and the metal-containing pattern, the metal-containing pattern including a bottom surface facing the gate pattern and opposite side surfaces extending from the bottom surface away from the gate pattern, a barrier pattern between the gate pattern and the metal-containing pattern, the barrier pattern formed of a nitride and extending along the opposite side surfaces of the metal-containing pattern, wherein the gate pattern is disposed both above and below a topmost surface of the active region, and a gate insulating pattern between a bottom surface of the gate pattern and the substrate, the gate insulating pattern additionally extending along opposite side surfaces of the gate pattern, and formed of a continuous material extending continuously from the bottom surface of the gate pattern to the first height to overlap the metal-containing pattern in a second direction parallel to the bottom surface of the substrate; and a pair of impurity regions disposed adjacent to opposite side surfaces of the gate structure such that the gate structure is at a height above a topmost portion of each impurity region and is at a height below a bottommost portion of each impurity region.