Samsung patents memory check method to speed up data writing

1. A memory device comprising: a memory cell array including a plurality of memory cells; a voltage generator configured to generate a program voltage and a verification voltage; and a control logic configured to control multiple program loops to program the plurality of memory cells, using the program voltage, to multiple program states during a data write operation and to determine, using the verification voltage, whether programming passes or fails in the multiple program loops, wherein the control logic is configured to control the multiple program loops to verify one or more (n+1)-th memory cells to be programmed to an (n+1)-th program state using a verification condition for verifying an n-th program state in at least one of the multiple program loops, wherein n is an integer greater than or equal to 1, wherein the multiple program loops include a first program loop to an A-th program loop, wherein A is an integer greater than or equal to 2, wherein whether the programming of the one or more (n+1)-th memory cells passes or fails during the first program loop to a B-th program loop is determined by using the verification voltage having a first level for verifying the n-th program state, wherein B is an integer greater than or equal to 1 and less than A, wherein the B-th program loop is a program loop wherein a verification of the programming of the one or more (n+1)-th memory cells to the n-th program state passes, wherein the memory device is configured to adjust the verification voltage from the first level to a second level based on the programming of the one or more (n+1)-th memory cells passing the verification using the verification voltage having the first level, and in a (B+1)-th program loop, whether the programming of the one or more (n+1)-th memory cells passes or fails is determined by using the verification voltage having the second level for verifying the (n+1)-th program state, and wherein the second level is different from the first level.