Samsung patents memory layout that splits address signals to speed up data access

1. A memory device comprising: a peripheral circuit structure; and a cell array structure provided on the peripheral circuit structure and overlapping the peripheral circuit structure in a vertical direction, wherein the cell array structure comprises a plurality of memory blocks arranged in a first horizontal direction, at least one of the plurality of memory blocks comprising: a memory cell region comprising a plurality of word lines extending in the first horizontal direction and a plurality of bit lines extending in a second horizontal direction perpendicularly crossing the first horizontal direction, wherein the peripheral circuit structure comprises a row decoder connected to the plurality of word lines of each of the plurality of memory blocks, and the row decoder comprises: a first circuit group configured to generate main word line driving signals and sub word line driving signals, the first circuit group being commonly connected to the plurality of memory blocks; and a second circuit group respectively connected to the plurality of memory blocks and configured to generate local main word line driving signals and local sub word line driving signals and activate one word line from among a plurality of word lines of a memory block selected from among the plurality of memory blocks, wherein row address signals of the row decoder are classified into a more significant bit group and a less significant bit group, and wherein the first circuit group comprises: a main word line driving signal generation circuit configured to generate first main word line driving signals and second main word line driving signals based on the row address signals that belong to the more significant bit group, wherein the main word line driving signals comprise the first main word line driving signals and the second main word line driving signals; and a sub word line driving signal generation circuit configured to generate first sub word line driving signals, second sub word line driving signals, and third sub word line driving signals based on the row address signals that belong to the less significant bit group among the row address signals, wherein the sub word line driving signals comprise the first sub word line driving signals, the second sub word line driving signals, and the third sub word line driving signals.