Samsung patents chip design that splits neural network tasks across memory blocks
Samsung describes a hardware design that divides a neural network's calculations across multiple memory blocks called cell tiles. The system stores the network's settings, or weights, in these blocks and splits input data into parts, sending different parts to different groups of blocks to process the information.
In the filing’s own words
A neuromorphic device includes a plurality of cell tiles, each of the plurality of cell tiles including a cell array including a plurality of memory cells storing weights of a neural network, a row driver connected to the plurality of memory cells through a plurality of row lines, and cell analog-digital converters (ADCs) connected to the plurality of memory cells through a plurality of column lines, and a controller configured to select, form the plurality of cell tiles, a plurality of valid cell tiles storing the weights, execute a neural network-based arithmetic operation based on the plurality of valid cell tiles, and redundantly store weights of a first layer among a plurality of layers included in the neural network in a plurality of first valid cell tiles that are divided into a plurality of first tile groups.
What exactly they claim (claim 1)
1. A neuromorphic device comprising: a plurality of cell tiles, each of the plurality of cell tiles comprising: a cell array comprising a plurality of memory cells storing weights of a neural network, a row driver connected to the plurality of memory cells through a plurality of row lines, and cell analog-to-digital converters (ADCs) connected to the plurality of memory cells through a plurality of column lines; and a controller configured to: select, form the plurality of cell tiles, a plurality of valid cell tiles storing the weights, execute a neural network-based arithmetic operation based on the plurality of valid cell tiles, redundantly store weights of a first layer among a plurality of layers included in the neural network in a plurality of first valid cell tiles that are divided into a plurality of first tile groups, input a lower bit of input data input to the first layer to a first tile group of the plurality of first tile groups, and input an upper bit of the input data to a second tile group of the plurality of first tile groups during the neural network-based arithmetic operation.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Neuromorphic device
- Patent number
- US12737600B2
- Application number
- 17983058
- Filed
- Nov 8, 2022
- Granted
- Sep 15, 2026
- Inventors
- 1
- Claims
- 20
Classified under
G06N 3/063 Physics & computingG06N 3/0495 Physics & computingG06N 3/065 Physics & computingG06N 3/048 Physics & computingG06N 3/08 Physics & computingMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.