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Samsung patents chip design that simplifies math using XNOR gates

This patent describes a hardware component called a multiplier-accumulator that performs calculations using specialized logic gates known as XNOR gates. It converts standard computer numbers into a simpler format with only positive and negative values to speed up the multiplication process. The design includes a correction step to ensure the final result is accurate after these simplified calculations.

Why it mattersThis is a specific engineering improvement for computer chips that could make certain calculations faster or more energy-efficient, though it is unlikely to be visible to everyday users.

In the filing’s own words

A multiplier-accumulator includes: a plurality of exclusive negative OR (XNOR) gates provided along one or more input lines and configured to receive signals corresponding to an input bit sequence and a weight bit sequence corresponding to each of the one or more input lines and to output partial product results between the input bit sequence and the weight bit sequence; an encoder configured to apply, to the plurality of XNOR gates, a signal corresponding to a sequence in which a logical value of a most significant bit (MSB) is converted from an original sequence expressed in 2's complement of a corresponding sequence for either one or both of the input bit sequence and the weight bit sequence; and an outputter configured to generate an output in which a correction value is applied to operation results in which the partial product results output from the plurality of XNOR gates are summed.

What exactly they claim (claim 1)

1. A multiplier-accumulator comprising: a plurality of exclusive negative OR (XNOR) gates provided along one or more input lines and configured to receive signals corresponding to an input bit sequence and a weight bit sequence corresponding to each of the one or more input lines and to output partial product results between the input bit sequence and the weight bit sequence; an encoder configured to apply, to the plurality of XNOR gates, a signal corresponding to a sequence in which a logical value of a most significant bit (MSB) is inverted from an original sequence expressed in 2's complement of a corresponding sequence for either one or both of the input bit sequence and the weight bit sequence; and an outputter configured to generate an output in which a correction value is applied to operation results in which the partial product results output from the plurality of XNOR gates are summed, wherein the original sequence expressed in 2's complement is inverted to a number system having bit values of only −1 and +1, the input bit sequence and the weight bit sequence are expressed in the number system having bit values of only −1 and +1, and wherein the encoder comprises an input encoder configured to: sequentially receive an original input sequence expressed in 2's complement of the input bit sequence for each bit position; and in response to receiving the MSB, apply a signal corresponding to a value in which the logical value of the MSB for the original input sequence is inverted to the plurality of XNOR gates provided to an input line of the one or more input lines corresponding to the input bit sequence.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
Computing device and method using multiplier-accumulator
Patent number
US12737154B2
Application number
17735492
Filed
May 3, 2022
Granted
Sep 15, 2026
Inventors
4
Claims
23

Classified under

G06F 7/5443 Physics & computingG06F 7/4824 Physics & computing
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.