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Samsung patents chip stack design with extra wiring layer for better connections

Samsung has been granted a patent for a semiconductor package that stacks multiple chips on a base called a buffer die. The top chip in each stack features a redistribution layer, which is an extra circuit board-like layer that helps route electrical signals to specific points on the chip's surface.

Why it mattersThis design improves how stacked chips connect to each other, which is a standard technique used to build more complex and efficient processors for phones and computers.

In the filing’s own words

A semiconductor package includes a buffer die, semiconductor chip stacks stacked on the buffer die, each of the semiconductor chip stacks including a plurality of first semiconductor chips and a second semiconductor chip on the plurality of first semiconductor chips, and a mold layer covering an upper surface of the buffer die and side surfaces of the semiconductor chip stacks. Each of the first semiconductor chips and the second semiconductor chip includes a wiring part including multilayer wirings, an upper connection structure on the wiring part and having a plurality of upper conductive pads and a lower connection structure under the wiring part and having a plurality of lower conductive pads, and the second semiconductor chip further includes a redistribution layer on the upper connection structure and having an insulating layer and a plurality of redistribution pads in the insulating layer.

What exactly they claim (claim 1)

1. A semiconductor package comprising: a buffer die; semiconductor chip stacks stacked on the buffer die, each of the semiconductor chip stacks including a plurality of first semiconductor chips and at least one second semiconductor chip on the plurality of first semiconductor chips; and a mold layer covering an upper surface of the buffer die and side surfaces of the semiconductor chip stacks, wherein each of the plurality of first semiconductor chips and the at least one second semiconductor chip includes: a wiring part including multilayer wirings; an upper connection structure on the wiring part and having a plurality of upper conductive pads; and a lower connection structure under the wiring part and having a plurality of lower conductive pads, and wherein the at least one second semiconductor chip further includes: a redistribution layer on the upper connection structure and having an insulating layer and a plurality of redistribution pads in the insulating layer; wherein the redistribution layer further includes a redistribution via in the insulating layer and connected to one of the plurality of redistribution pads thereunder, and wherein in a corresponding semiconductor chip stack of the semiconductor chip stacks, a number of the redistribution layer is equal to a number of the at least one second semiconductor chip in the corresponding semiconductor chip stack.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
Semiconductor package
Patent number
US12733549B2
Application number
18312331
Filed
May 4, 2023
Granted
Sep 8, 2026
Inventors
2
Claims
20

Classified under

H10W 90/00 Electricity & electronicsH10B 80/00 Electricity & electronicsH10W 20/42 Electricity & electronicsH10W 74/111 Electricity & electronicsH10W 90/792 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.