Samsung patents chip package design with specific bump structures
Samsung has secured a patent for a semiconductor package that uses a redistribution layer to connect chips on one side to an interconnect chip on the other. The design features specific bump structures with foil and plating layers that connect the internal circuitry to the outside of the package.
In the filing’s own words
A semiconductor package includes: a substrate including a redistribution member having a first surface and a second surface, opposing each other, and including pad structures disposed on the first surface and a redistribution layer electrically connected to the pad structures, an interconnect chip disposed on the second surface of the redistribution member and including an interconnect circuit electrically connected to the redistribution layer, a via structure disposed around the interconnect chip and electrically connected to the redistribution layer, an encapsulant encapsulating at least a portion of each of the interconnect chip and the via structure, and bump structures disposed on the encapsulant; and a first chip structure and a second chip structure disposed on the first surface of the redistribution member and electrically connected to the pad structures.
What exactly they claim (claim 1)
1. A semiconductor package comprising: a substrate including a redistribution member, wherein the redistribution member comprises a first surface and a second surface opposite of the first surface, pad structures disposed on the first surface, and a redistribution layer electrically connected to the pad structures, an interconnect chip disposed on the second surface of the redistribution member and including an interconnect circuit electrically connected to the redistribution layer, a via structure disposed around the interconnect chip and electrically connected to the redistribution layer, an encapsulant encapsulating at least a portion of each of the interconnect chip and the via structure, and bump structures disposed on the encapsulant; and a first chip structure and a second chip structure disposed on the first surface of the redistribution member and electrically connected to the pad structures, wherein the bump structures include a first bump structure, overlapping at least a portion of the interconnect chip in a first direction that is perpendicular to the second surface, and a second bump structure overlapping at least a portion of the via structure, the first bump structure includes a first foil layer that is disposed on the encapsulant and includes a first plating layer disposed on the first foil layer, and the second bump structure includes a second foil layer that is disposed on the encapsulant and includes a second plating layer disposed in an opening penetrating through the second foil layer to expose at least a portion of the via structure.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Semiconductor package and method of manufacturing the same
- Patent number
- US12733547B2
- Application number
- 18298702
- Filed
- Apr 11, 2023
- Granted
- Sep 8, 2026
- Inventors
- 3
- Claims
- 15
Classified under
H10W 90/00 Electricity & electronicsH10B 80/00 Electricity & electronicsH10W 20/042 Electricity & electronicsH10W 70/635 Electricity & electronicsH10W 74/114 Electricity & electronicsH10W 90/401 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.