Samsung patents chip stacking design using empty pads for better alignment
Samsung has been granted a patent for a semiconductor package that stacks two layers of chips together. The design includes 'dummy pads,' which are empty metal spots placed between the active signal connections, to help align the layers precisely.
In the filing’s own words
Disclosed is a semiconductor package comprising lower and upper structure. The lower structure includes a first semiconductor substrate, first through vias vertically penetrating the first semiconductor substrate, first signal pads connected to the first through vias, first dummy pads between the first signal pads and electrically separated from the first through vias, and a first dielectric layer surrounding the first signal pads and the first dummy pads. The upper structure includes a second semiconductor substrate, second signal pads and second dummy pads, and a second dielectric layer surrounding the second signal pads and the second dummy pads. The first signal pad is in contact with one of the second signal pads. The first dummy pad is in contact with one of the second dummy pads. A first interval between the first dummy pads is 0.5 to 1.5 times a second interval between the first signal pads.
What exactly they claim (claim 1)
1. A semiconductor package, comprising: a lower structure; and an upper structure on the lower structure, wherein the lower structure includes: a first semiconductor substrate; first through vias that vertically penetrate the first semiconductor substrate; first signal pads on the first semiconductor substrate, wherein the first signal pads are connected to the first through vias; first dummy pads on the first semiconductor substrate, wherein the first dummy pads are disposed between the first signal pads in a plan view, and the first dummy pads are electrically separated from the first through vias; and a first dielectric layer on the first semiconductor substrate, wherein the first dielectric layer surrounds the first signal pads and the first dummy pads, wherein the upper structure includes: a second semiconductor substrate; second signal pads and second dummy pads on the second semiconductor substrate; and a second dielectric layer on the second semiconductor substrate, wherein the second dielectric layer surrounds the second signal pads and the second dummy pads, wherein each of the first signal pads is in contact with one of the second signal pads, wherein each of the first dummy pads is in contact with one of the second dummy pads, and wherein a first interval between the first dummy pads is about 0.5 times to about 1.5 times a second interval between the first signal pads.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Semiconductor package with dummy pads
- Patent number
- US12733475B2
- Application number
- 18234529
- Filed
- Aug 16, 2023
- Granted
- Sep 8, 2026
- Inventors
- 6
- Claims
- 19
Classified under
H10W 20/20 Electricity & electronicsH10W 72/926 Electricity & electronicsH10W 72/934 Electricity & electronicsH10W 72/936 Electricity & electronicsH10W 72/967 Electricity & electronicsH10W 90/792 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.