Samsung patents chip design with fins of different widths
Samsung has secured a patent for a semiconductor structure that uses 'fins' of varying widths to control electrical flow. The design places different gate lines over these wide and narrow sections to manage how the chip's transistors operate.
In the filing’s own words
A semiconductor device is provided, the semiconductor device including; a substrate; a first fin structure extending on the substrate in a first direction, and having a first fin portion having a first width and a second fin portion having a second width; a second fin structure extending on the substrate in the first direction, and having the second width; first gate lines disposed on the first fin portion and the second fin structure, and extending in a second direction; second gate lines disposed on the second fin portion and the second fin structure, and extending in the second direction; a third gate line disposed on the second fin structure, and extending in the second direction between the first and second gate lines; and a device isolation pattern connected to an end portion of the third gate, and extending between the first and second fin portions.
What exactly they claim (claim 1)
1. A semiconductor device, comprising: a substrate; a first fin structure extending on the substrate in a first direction, and having a first fin portion having a first width in a second direction crossing the first direction and a second fin portion having a second width in the second direction, greater than the first width; a second fin structure extending on the substrate in the first direction, and having the second width in the second direction; a plurality of first gate lines that comprises a first gate line, on the first fin portion of the first fin structure and the second fin structure, wherein the plurality of first gate lines is extending in the second direction; a plurality of second gate lines that comprises a second gate line, on the second fin portion of the first fin structure and the second fin structure, wherein the plurality of second gate lines is extending in the second direction; a third gate line on the second fin structure, wherein the third gate line is extending in the second direction between the first gate line and the second gate line, wherein the first gate line, the second gate line, and the third gate line control active regions of the semiconductor device; and a device isolation pattern connected to an end portion of the third gate line, and extending between the first fin portion of the first fin structure and the second fin portion of the first fin structure.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Semiconductor device including a plurality of gate lines on a plurality of fin structures having different width portions
- Patent number
- US12733249B2
- Application number
- 18365452
- Filed
- Aug 4, 2023
- Granted
- Sep 8, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10D 84/83 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 62/121 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.