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Samsung patents chip design with specific spacing for backside contacts

Samsung describes a semiconductor layout where electrical connections on the back of a chip are separated by insulating barriers. The design specifies that these barriers and connections must be spaced evenly apart to fit within the chip's structure.

Why it mattersThis is a detailed technical specification for manufacturing chips, focusing on how to arrange internal components to prevent electrical interference.

In the filing’s own words

Provided is a semiconductor device including: a 1 st source/drain region and a 1 st backside contact structure, vertically below the 1 st source/drain region, connected to the 1 st source/drain region; a 2 nd source/drain region and a 1 st placeholder isolation structure vertically below the 2 nd source/drain region; and a backside isolation structure, on a back side of the semiconductor device, surrounding the 1st backside contact structure and the 1st placeholder isolation structure.

What exactly they claim (claim 1)

1. A semiconductor device comprising: a 1 st source/drain region and a 1 st backside contact structure, vertically below the 1 st source/drain region, connected to the 1 st source/drain region; a 2 nd source/drain region and a 1 st placeholder isolation structure vertically below the 2 nd source/drain region; a backside isolation structure, on a back side of the semiconductor device, surrounding the 1 st backside contact structure and the 1 st placeholder isolation structure; and a 3 rd source/drain region and a 2 nd placeholder isolation structure vertically below the 3 rd source/drain region, wherein the 2 nd source/drain region is between the 1 st source/drain region and the 3 rd source/drain region, and wherein a horizontal distance between the 1 st backside contact structure and the 1 st placeholder isolation structure is equal to a horizontal distance between the 1 st placeholder isolation structure and the 2 nd placeholder isolation structure.

Facts

Company
Samsung (SAMSUNG ELECTRONICS CO., LTD.)
Official title
Semiconductor device including backside isolation structure and placeholder isolation structure
Patent number
US12733219B2
Application number
18214221
Filed
Jun 26, 2023
Granted
Sep 8, 2026
Inventors
3
Claims
20

Classified under

H10D 62/116 Electricity & electronicsH10D 8/411 Electricity & electronicsH10D 30/43 Electricity & electronicsH10D 30/6735 Electricity & electronicsH10D 30/6757 Electricity & electronicsH10D 62/121 Electricity & electronics

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.