Samsung patents transistor design with dual voltage control layers
This patent describes a specific layout for a transistor, a tiny switch used in computer chips. It features a gate structure with two separate conductive patterns designed to adjust the voltage needed to turn the switch on or off. The design also includes a layered drain region with different levels of impurity doping to manage how electricity flows through the device.
In the filing’s own words
A transistor includes a substrate including a P-type-sub region doped with P-type impurities, a well region positioned at an upper portion of the substrate and doped with P-type impurities, a gate structure on the well region, and drain and source regions. The gate structure includes a gate insulation layer, first and second conductive patterns for adjusting a threshold voltage and a gate electrode. The drain and source regions are positioned at an upper portion of the substrate adjacent first and second sidewalk of the gate structure, respectively. The source region is doped with N-type impurities. The drain region includes a highly doped N-type impurity region, an N-type impurity region, and a lightly doped P-type impurity region sequentially disposed in a downward direction from a top surface of the substrate. A boundary between the well region and the P-type sub region is positioned under a bottom of the drain region.
What exactly they claim (claim 1)
1. A transistor, comprising: a substrate having a bulk region including a P-type-sub region that is doped with P-type impurities; a well region positioned at an upper portion of the substrate, the well region is doped with P-type impurities; a gate structure on the well region; the gate structure including a gate insulation layer, a first conductive pattern for adjusting a threshold voltage; a second conductive pattern for adjusting a threshold voltage, and a gate electrode; a drain region positioned at an upper portion of the substrate adjacent to a first sidewall of the gate structure; and a source region doped with N-type impurities and positioned at an upper portion of the substrate adjacent to a second sidewall of the gate structure, the second sidewall of the gate structure facing the first sidewall of the gate structure; an additional impurity region protruding from one sidewall of the drain region towards the source region, wherein the additional impurity region is doped with N-type impurities, and is spaced apart from an upper surface of the substrate; wherein the drain region includes a highly doped N-type impurity region; an N-type impurity region having a lower N-type impurity concentration than the highly doped N-type impurity region, and a lightly doped P-type impurity region sequentially disposed in a downward direction from a top surface of the substrate towards a bottom surface of the substrate, wherein a boundary between the well region and the P-type-sub region is positioned under a bottom of the drain region, and wherein a first portion of the lightly doped P-type impurity region of the drain region directly contacts the P-type-sub region, and a second portion of the lightly doped P-type impurity region of the drain region directly contacts the well region.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Transistor
- Patent number
- US12733202B2
- Application number
- 18092246
- Filed
- Dec 31, 2022
- Granted
- Sep 8, 2026
- Inventors
- 3
- Claims
- 18
Classified under
H10D 30/65 Electricity & electronicsH10D 30/0281 Electricity & electronicsH10D 30/6211 Electricity & electronicsH10D 62/157 Electricity & electronicsH10D 64/01318 Electricity & electronicsH10D 64/017 Electricity & electronicsMore from Samsung in Chips & hardware
- Samsung patents chip that combines camera and screen Oct 13, 2026
- Samsung patents faster chip testing using machine learning Sep 1, 2026
- Samsung patents radar method to pinpoint target direction more accurately Sep 1, 2026
- Samsung patents memory chip that searches data by content, not address Sep 1, 2026
- Samsung patents chip design that skips empty data to speed up AI Sep 1, 2026
Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.