Samsung patents 3D memory stacking high and low voltage parts
This patent describes a 3D memory device where the storage cells sit on one chip, while the control circuits are split across two other chips stacked on top. One top chip handles high-voltage tasks, and the other handles low-voltage tasks, allowing the components to be separated by their power needs.
In the filing’s own words
A memory device is provided. The memory device includes: a memory cell array implemented in a first chip; and a peripheral circuit implemented in a second chip and a third chip which overlaps the first chip along a vertical direction. The peripheral circuit includes: a first peripheral circuit implemented in the second chip and the third chip; a second peripheral circuit implemented in the second chip and including at least one high-voltage transistor; and a third peripheral circuit implemented in the third chip and including at least one low-voltage transistor. The first peripheral circuit includes: a first sub-peripheral circuit implemented in the second chip and including at least one high-voltage transistor; and a second sub-peripheral circuit implemented in the third chip and including at least one low-voltage transistor.
What exactly they claim (claim 1)
1. A memory device comprising: a memory cell array implemented in a first chip; and a peripheral circuit implemented in a second chip and a third chip which overlaps the first chip when viewed in a plan view, wherein the peripheral circuit comprises: a first peripheral circuit implemented in the second chip and the third chip; a second peripheral circuit implemented in the second chip and comprising at least one high-voltage transistor; and a third peripheral circuit implemented in the third chip and comprising at least one low-voltage transistor, and wherein the first peripheral circuit comprises: a first sub-peripheral circuit implemented in the second chip and comprising at least one high-voltage transistor; and a second sub-peripheral circuit implemented in the third chip and comprising at least one low-voltage transistor.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Three-dimensional memory device
- Patent number
- US12733173B2
- Application number
- 18897719
- Filed
- Sep 26, 2024
- Granted
- Sep 8, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10B 43/40 Electricity & electronicsG11C 5/063 Physics & computingG11C 16/0483 Physics & computingG11C 16/10 Physics & computingG11C 16/26 Physics & computingH10B 41/27 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.