Samsung patents vertical chip design with specific layer stacking
This patent describes a vertical semiconductor device where gate electrodes and insulation layers are stacked on a substrate. It details a specific arrangement of channel structures, including doped and undoped semiconductor layers, around a gate electrode used for erasing data.
In the filing’s own words
A vertical semiconductor device includes; a pattern structure including a plurality of insulation patterns and a plurality of gate electrodes that are alternately and repeatedly stacked on a substrate, wherein the pattern structure includes a first gate electrode serving as a gate electrode of an erase transistor, wherein the first gate electrode is one of the plurality of gate electrodes; and a channel structure in a channel hole passing through the pattern structure, wherein the channel structure includes a data storage structure, a first channel, an undoped semiconductor liner, a doped semiconductor pattern, a filling insulation pattern and a capping pattern, wherein the data storage structure, the first channel, the undoped semiconductor liner, and the doped semiconductor pattern are sequentially disposed on a sidewall of the first gate electrode.
What exactly they claim (claim 1)
1. A vertical semiconductor device, comprising: a pattern structure including a plurality of insulation patterns and a plurality of gate electrodes that are alternately and repeatedly stacked on a substrate, wherein the pattern structure includes a first gate electrode serving as a gate electrode of an erase transistor, wherein the first gate electrode is one of the plurality of gate electrodes, a channel structure in a channel hole passing through the pattern structure, wherein the channel structure includes a data storage structure, a first channel, an undoped semiconductor liner, a doped semiconductor pattern, a filling insulation pattern and a capping pattern; and an upper base pattern including doped poly silicon disposed on the pattern structure, and wherein the upper base pattern contacts the first channel, the doped semiconductor pattern, the undoped semiconductor liner and an uppermost insulation pattern, wherein the doped semiconductor pattern has a pillar shape, and the undoped semiconductor liner surrounds an outer sidewall and bottom of the doped semiconductor pattern, wherein a vertical portion of the undoped semiconductor liner contacts the first channel and a horizontal portion of the undoped semiconductor liner contacts the filling insulation pattern, and wherein the data storage structure, the first channel, the undoped semiconductor liner, and the doped semiconductor pattern are sequentially disposed on a sidewall of the first gate electrode.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Bonding type vertical semiconductor devices
- Patent number
- US12733167B2
- Application number
- 18243200
- Filed
- Sep 7, 2023
- Granted
- Sep 8, 2026
- Inventors
- 5
- Claims
- 15
Classified under
H10B 43/27 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.