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Samsung patents 3D memory chip design with internal separation zones

Samsung describes a 3D memory chip where the stacked layers are physically cut into separate sections using insulating lines. This design creates a distinct separation region between different parts of the memory stack to manage electrical connections.

Why it mattersThis is a routine improvement in chip manufacturing that helps manage the complexity of stacking memory layers, potentially improving reliability for future storage devices.

In the filing’s own words

A three-dimensional semiconductor memory device may include a substrate including a first connection region, a first cell region, a separation region, a second cell region, and a second connection region, which are sequentially disposed in a first direction, a stack structure including electrode layers and insulating layers, which are alternately stacked on the substrate, the electrode layers including upper electrode layers, a first insulating line pattern on the separation region to penetrate the upper electrode layers and extend in a second direction crossing the first direction, second and third insulating line patterns on the separation region to penetrate the first insulating line pattern and the stack structure and to extend in the second direction to divide the stack structure into first and second sub-stack structures, and a remaining stack structure between the second and third insulating line patterns and spaced apart from the first and second sub-stack structures.

What exactly they claim (claim 1)

1. A three-dimensional semiconductor memory device, comprising: a substrate including a first connection region, a first cell region, a separation region, a second cell region, and a second connection region, which are sequentially disposed in a first direction; a stack structure including electrode layers and electrode interlayer insulating layers, which are alternately stacked on the substrate, the electrode layers including upper electrode layers; a first insulating line pattern on the separation region, the first insulating line pattern penetrating the upper electrode layers and extending in a second direction crossing the first direction; a second insulating line pattern and a third insulating line pattern on the separation region, the second insulating line pattern and the third insulating line pattern penetrating the first insulating line pattern and the stack structure, and extending in the second direction to divide the stack structure into a first sub-stack structure and a second sub-stack structure; and a remaining stack structure between the second insulating line pattern and the third insulating line pattern, the remaining stack structure being spaced apart from the first sub-stack structure and the second sub-stack structure, wherein a top surface of the first insulating line pattern is lower than top surfaces of the second insulating line pattern and the third insulating line pattern, and wherein a bottom surface of the first insulating line pattern is higher than bottom surfaces of the second insulating line pattern and the third insulating line pattern.

Facts

Company
Samsung (SAMSUNG ELECTRONICS CO., LTD.)
Official title
Three-dimensional semiconductor memory device including separation region and electronic system including the same
Patent number
US12733166B2
Application number
18080916
Filed
Dec 14, 2022
Granted
Sep 8, 2026
Inventors
2
Claims
20

Classified under

H10B 43/27 Electricity & electronicsH10B 41/27 Electricity & electronicsH10B 41/41 Electricity & electronicsH10B 43/10 Electricity & electronicsH10B 43/40 Electricity & electronicsH10B 43/50 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.