Samsung patents chip design with a specific gate spacer shape
This filing describes a specific layout for the gate structure inside a semiconductor chip. It uses a layered insulating material with a recessed area and a metal layer, where a spacer component fits into that recess to cover the side of the gate.
In the filing’s own words
A semiconductor device includes a substrate including a peripheral active pattern defined by a device isolation layer, a gate structure on the peripheral active pattern, and a gate spacer covering at least a portion of a side surface of the gate structure. The gate structure includes an insulating pattern structure and a metal pattern structure on the insulating pattern structure. The insulating pattern structure includes a recess having a maximum depth in a first direction parallel to a top surface of the substrate at a first height. The insulating pattern structure includes a first gate insulating pattern and a high-k dielectric layer, which are sequentially stacked on the top surface of the substrate. The gate spacer includes a protrusion inserted in the recess.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a substrate including a peripheral active pattern defined by a device isolation layer; a gate structure on the peripheral active pattern; and a gate spacer covering at least a portion of a side surface of the gate structure, wherein the gate structure comprises an insulating pattern structure and a metal pattern structure on the insulating pattern structure, wherein the insulating pattern structure includes a recess having a maximum depth in a first direction parallel to a top surface of the substrate at a first height, wherein the insulating pattern structure comprises a first gate insulating pattern and a high-k dielectric layer, which are sequentially stacked on the top surface of the substrate, and wherein the gate spacer includes a protrusion in the recess, wherein the first height is higher than a height of an upper surface of the first gate insulating pattern.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Semiconductor device
- Patent number
- US12733160B2
- Application number
- 18456655
- Filed
- Aug 28, 2023
- Granted
- Sep 8, 2026
- Inventors
- 9
- Claims
- 20
Classified under
H10B 12/50 Electricity & electronicsH10B 12/315 Electricity & electronicsH10B 12/482 Electricity & electronicsH10B 12/485 Electricity & electronicsH10B 12/488 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.