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Samsung patents 3D memory layout that stacks circuits under cells

Samsung describes a semiconductor design where sense amplifier and column circuits are placed directly underneath the memory cell array. This vertical stacking allows bit lines to run over the lower circuits, creating a denser structure for storing data.

Why it mattersThis layout technique helps manufacturers pack more memory into a smaller chip, which is a standard improvement for increasing storage capacity in devices.

In the filing’s own words

A semiconductor device includes a BLSA circuit pattern on a substrate, a column circuit pattern on a portion of the substrate adjacent to the BLSA pattern, and a cell array. The cell array includes bit lines extending in a first direction and spaced apart from each other in a second direction on the BLSA circuit pattern and the column circuit pattern, gate electrodes extending in the second direction and spaced apart from each other in the first direction, a gate insulation pattern on a sidewall in the first direction of the gate electrode, a channel on a sidewall in the first direction of the gate insulation pattern and contacting the bit line, a landing pad on the channel, and a capacitor on the landing pad. The BLSA circuit pattern and the column circuit pattern overlap the cell array in a vertical direction.

What exactly they claim (claim 1)

1. A semiconductor device comprising: a bit line sense amplifier (BLSA) circuit pattern on a substrate; a column circuit pattern on the substrate adjacent to the BLSA pattern; and a cell array including: bit lines on the BLSA circuit pattern and the column circuit pattern, each of the bit lines extending in a first direction and spaced apart from each other in a second direction crossing the first direction; gate electrodes spaced apart from each other in the first direction, each of the gate electrodes extending in the second direction on the bit lines; a gate insulation pattern on a sidewall in the first direction of each of the gate electrodes; a channel on a sidewall in the first direction of the gate insulation pattern, the channel contacting a corresponding one of the bit lines; a landing pad on the channel, where the gate insulation pattern extends to a sidewall of a lower portion of the landing pad; and a capacitor on the landing pad, wherein the BLSA circuit pattern and the column circuit pattern overlap the cell array in a third direction substantially perpendicular to the first and second directions.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
Semiconductor devices
Patent number
US12733159B2
Application number
18448290
Filed
Aug 11, 2023
Granted
Sep 8, 2026
Inventors
2
Claims
20

Classified under

H10B 12/50 Electricity & electronicsH10B 12/033 Electricity & electronicsH10B 12/05 Electricity & electronicsH10B 12/315 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.