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Samsung patents 3D memory chip design without capacitors

Samsung has been granted a patent for a semiconductor memory device that stacks memory cells in a three-dimensional structure. Each memory cell uses two transistors and two bit lines to store data, eliminating the need for a traditional capacitor component.

Why it mattersThis design could potentially make memory chips smaller or more efficient by removing capacitors, though it remains a technical improvement for internal hardware.

In the filing’s own words

A semiconductor memory device includes a memory cell array having a three-dimensional structure, the memory cell array including a plurality of memory cells repeatedly arranged in a first lateral direction, a second lateral direction, and a vertical direction, wherein the first lateral direction and the second lateral direction are perpendicular to each other, and the vertical direction is perpendicular to each of the first lateral direction and the second lateral direction, wherein each of the plurality of memory cells includes two transistors including at a least portions of two word lines passing through the memory cell in the vertical direction and at least portions of two bit lines respectively on both sides of the two word lines in the first lateral direction, each of the two bit line extending along the second lateral direction, and each of the plurality of memory cells does not include a capacitor.

What exactly they claim (claim 1)

1. A semiconductor memory device comprising: a memory cell array having a three-dimensional structure, the memory cell array comprising a plurality of memory cells, the plurality of memory cells being repeatedly arranged in a first lateral direction, a second lateral direction, and a vertical direction, wherein the first lateral direction and the second lateral direction are perpendicular to each other, and the vertical direction is perpendicular to each of the first lateral direction and the second lateral direction, wherein each of the plurality of memory cells comprises two transistors comprising at least portions of two word lines passing through the memory cell in the vertical direction and at least portions of two bit lines respectively on both sides of the two word lines in the first lateral direction, each of the two bit lines extending along in the second lateral direction, and each of the plurality of memory cells does not comprise a capacitor.

Facts

Company
Samsung (Samsung Electronics Co., Ltd.)
Official title
Semiconductor memory device
Patent number
US12733155B2
Application number
18421187
Filed
Jan 24, 2024
Granted
Sep 8, 2026
Inventors
4
Claims
20

Classified under

H10B 12/488 Electricity & electronicsH10B 12/482 Electricity & electronicsH10D 62/221 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.