Samsung patents chip gate design with a wider middle section
This patent describes a specific shape for the control structure, or gate, inside a semiconductor chip. The gate is built in a trench and has a middle section that is wider than both its top and bottom parts.
In the filing’s own words
A semiconductor device includes an active region, an isolation region on a side surface of the active region, a gate trench having a first trench portion crossing the active region and a second trench portion in the isolation region, a first gate portion within the first trench portion and a second gate portion within the second trench portion. The first gate portion and the second gate portion each includes a gate dielectric layer, a gate electrode on the gate dielectric layer, partially filling the gate trench, and having an upper surface disposed on a level lower than an upper end of the active region, and an insulative capping pattern on the gate electrode. The first gate portion includes a lower region, an intermediate region on the lower region, and an upper region on the intermediate region. A maximum width of the intermediate region is greater than a maximum width of the lower region and greater than a maximum width of the upper region.
What exactly they claim (claim 1)
1. A semiconductor device comprising: a semiconductor substrate; an active region on the semiconductor substrate; an isolation region on the semiconductor substrate, wherein the isolation region is on a side surface of the active region; a first trench portion crossing the active region; a second trench portion disposed in the isolation region; a first gate portion within the first trench portion; and a second gate portion within the second trench portion, wherein the first gate portion includes: a first gate dielectric layer on an inner wall of the first trench portion; a first gate electrode on the first gate dielectric layer, wherein the first gate electrode partially fills the first trench portion, and has an upper surface at a level lower than an upper surface of the active region; and a first insulating capping pattern on the first gate electrode, wherein the second gate portion includes: a second gate dielectric layer on an inner wall of the second trench portion; a second gate electrode on the second gate dielectric layer, wherein the second gate electrode partially fills the second trench portion, and has an upper surface at a level lower than an upper surface of the active region; and a second insulating capping pattern on the second gate electrode, wherein the first gate portion includes a first lower region, a first intermediate region on the first lower region, and a first upper region on the first intermediate region, wherein in a first direction, a maximum width of the first intermediate region is greater than a maximum width of the first lower region, and wherein in the first direction, the maximum width of the first intermediate region is greater than a maximum width of the first upper region.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Semiconductor device including gate structure
- Patent number
- US12733150B2
- Application number
- 18435680
- Filed
- Feb 7, 2024
- Granted
- Sep 8, 2026
- Inventors
- 4
- Claims
- 20
Classified under
H10B 12/34 Electricity & electronicsH10D 62/115 Electricity & electronicsH10D 64/513 Electricity & electronicsMore from Samsung in Chips & hardware
- Samsung patents chip that combines camera and screen Oct 13, 2026
- Samsung patents faster chip testing using machine learning Sep 1, 2026
- Samsung patents radar method to pinpoint target direction more accurately Sep 1, 2026
- Samsung patents memory chip that searches data by content, not address Sep 1, 2026
- Samsung patents chip design that skips empty data to speed up AI Sep 1, 2026
Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.