Samsung patents memory chip design that adjusts signal timing for better reliability
This patent describes a memory device that uses a controller to synchronize and slightly delay specific control signals. By aligning these signals with the internal clock, the chip ensures commands are read correctly before being processed.
In the filing’s own words
Provided is a memory device including a chip select (CS) buffer that is configured to output a first internal chip selection signal, a command clock (CK) buffer that is configured to output an internal clock signal, a command/address (CA) buffer that that is configured to output a first internal command/address signal, a CA buffer controller configured to control on/off of the CA buffer based on the first internal chip selection signal, synchronize the first internal chip selection signal and the first internal command/address signal to the internal clock signal, and delay the phase of a second internal chip selection signal synchronized to the internal clock signal, and a command decoder configured to decode any one of the second internal chip selection signal, a phase-delayed third internal chip selection signal, and/or a second internal command/address signal synchronized with the internal clock signal.
What exactly they claim (claim 1)
1. A memory device comprising: a chip selection (CS) buffer configured to receive a chip selection signal and output a first internal chip selection signal; a clock (CK) signal buffer configured to receive a clock signal and output an internal clock signal; a command/address (CA) buffer configured to receive a command/address signal and output a first internal command/address signal; a CA buffer controller configured to control on/off of the CA buffer based on the first internal chip selection signal, synchronize the first internal chip selection signal and the first internal command/address signal to the internal clock signal, and delay a phase of a second internal chip selection signal to synchronize to the internal clock signal; and a command decoder configured to decode a phase-delayed third internal chip selection signal and a second internal command/address signal that is synchronized with the internal clock signal, and configured to generate an internal command.
Facts
- Company
- Samsung (Samsung Electronics Co., Ltd.)
- Official title
- Memory device and method of operating the same
- Patent number
- US12731631B2
- Application number
- 18937180
- Filed
- Nov 5, 2024
- Granted
- Sep 8, 2026
- Inventors
- 2
- Claims
- 20
Classified under
G11C 11/4076 Physics & computingG11C 11/4093 Physics & computingG11C 11/4096 Physics & computingG11C 11/4082 Physics & computingMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.