Samsung patents memory controller using four-phase signals for stacked chips
Samsung has been granted a patent for a memory controller designed to work with vertically stacked semiconductor dies. The system uses a logic die that generates four distinct output signals with different phases by synchronizing them with specific clock signals and their inverted versions. These signals are sent through vertical connections called through-silicon vias (TSVs) to manage data operations within the memory core.
In the filing’s own words
A semiconductor device includes at least one core die including a memory cell array, and a logic die configured to communicate with the at least one core die, the logic die includes first through fourth TSV circuit blocks including circuits each arranged in response to at least one TSV and configured to generate first through fourth output signals having different phases from each other, in which the first TSV circuit block generates the first output signal in synchronization with a first clock signal, the second TSV circuit block generates the second output signal in synchronization with a second clock signal, the third TSV circuit block generates the third output signal in synchronization with a clock signal obtained by inverting the first clock signal, and the fourth TSV circuit block generates the fourth output signal in synchronization with a clock signal obtained by inverting the second clock signal.
What exactly they claim (claim 1)
1. A semiconductor device comprising: at least one core die including a memory cell array; and a logic die configured to communicate with the at least one core die via a plurality of through silicon vias (TSVs), wherein the logic die comprises: a memory controller configured to control a memory operation on the at least one core die; first, second, third, and fourth TSV circuit blocks each configured to receive at least one of first, second, third, or fourth input signals, and generate at least one of first, second, third, or fourth output signals having different phases from each other and transmitted to the at least one core die via the TSVs; and a multi-phase clock generator configured to generate a first clock signal and a second clock signal having different phases from each other, provide the first clock signal to the first TSV circuit block and the third TSV circuit block, and provide the second clock signal to the second TSV circuit block and the fourth TSV circuit block, wherein the first TSV circuit block is configured to generate the first output signal in synchronization with the first clock signal, wherein the second TSV circuit block is configured to generate the second output signal in synchronization with the second clock signal, wherein the third TSV circuit block is configured to generate the third output signal in synchronization with an inverted first clock signal that is an inverted form of the first clock signal, and wherein the fourth TSV circuit block is configured to generate the fourth output signal in synchronization with an inverted second clock signal that is an inverted form of the second clock signal.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- Memory controller communicating with vertically stacked dies and semiconductor device including the same
- Patent number
- US12731622B2
- Application number
- 18955618
- Filed
- Nov 21, 2024
- Granted
- Sep 8, 2026
- Inventors
- 4
- Claims
- 20
Classified under
G11C 7/1066 Physics & computingG11C 7/222 Physics & computingH03L 7/0814 Electricity & electronicsMore from Samsung in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.