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Microsoft patents faster text parsing circuit for computers

Microsoft describes a hardware design that speeds up how computers read and interpret text. It uses a specific circuit layout to process multiple characters at once, which reduces the time needed to figure out the next step in the parsing process.

Why it mattersThis is a low-level engineering improvement that could make software run slightly faster, but it is unlikely to be noticeable to everyday users.

In the filing’s own words

The performance of a text parser implemented with a state machine is improved by reducing a critical dependence path. In one aspect, all possible current states for a given text input are read from a state table circuit, and the correct next state and output are then selected therefrom by an output multiplexer based on the current state, removing dependence on the current state from the table read, and allowing the read(s) to be pipelined. Further, multiple input units are configured to operate on multiple text characters in parallel, with each input unit propagating outputs for its state table circuit to the next downstream input unit. Each downstream input unit is configured to use the propagated states to provide the proper outputs to appropriates multiplexer inputs. The number of possible output states may be dynamically reduced, thereby reducing the size of the output multiplexer needed to select the next state.

What exactly they claim (claim 1)

1. A circuit-based text parser configured to process multiple input characters from a stream of characters in parallel, comprising: a state machine that: receives a stream of characters in sequence, the stream of characters comprising a first character and a second character; utilizes a set of state table circuits to select, based on the first character and a first predetermined state of a set of predetermined states and without a value of a current state of the text parser as input, a first possible state from a first state table circuit of the set of state table circuits and to select, based on the first character and a second predetermined state of the set of predetermined states and without the value of the current state as input, a second possible state from a second state table circuit of the set of state table circuits, the selection of the first possible state and the selection of the second possible state removing a dependence of state table reads on the current state; pipelines the second character utilizing the set of state table circuits; and utilizes an iteration interval circuit to select a first text parser output from among the first possible state and the second possible state in a reduced iteration interval based on the current state.

Facts

Company
Microsoft (Microsoft Technology Licensing, LLC)
Official title
High-performance microcoded text parser
Patent number
US12730965B2
Application number
18629057
Filed
Apr 8, 2024
Granted
Sep 8, 2026
Inventors
2
Claims
20

Classified under

G06F 40/205 Physics & computingG06F 16/83 Physics & computingH03K 19/1737 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.