Microsoft patents method to wipe chip memory for security
This patent describes a method for a security processor to clear data from a computer chip's internal memory and logic components. It uses built-in test circuits to write specific data patterns into these parts, effectively erasing their previous state.
In the filing’s own words
Systems and methods for state clearing of internal memory and flip-flops of a system using built-in test and scan circuitry are provided. A method includes a security processor: (1) fetching memory built-in self-test (MBIST) data and providing the MBIST data to an internal field-test (IFT) controller such that the IFT controller can drive the MBIST data via an IJTAG network to respective MBIST controllers, and (2) fetching scan data and providing the scan data to the IFT controller such that the IFT controller can drive the scan data via a scan network to respective embedded deterministic test (EDT) controllers. The method further includes each of the respective MBIST controllers state clearing respective internal memories by writing pertinent MBIST data into the respective internal memories. The method further includes each of the respective EDT controllers state clearing respective flip-flops by writing pertinent scan data into the respective flip-flops.
What exactly they claim (claim 1)
1. A method for state clearing of internal memories and flip-flops of a system for a security reason, the method comprising: a security processor fetching memory built-in self-test (MBIST) data and providing the MBIST data to an internal field-test (IFT) controller associated with the system such that the IFT controller can drive the MBIST data via an internal joint test action group (IJTAG) network to respective MBIST controllers within the system; the security processor fetching scan data and providing the scan data to the IFT controller such that the IFT controller can drive the scan data via a scan network to respective embedded deterministic test (EDT) controllers within the system; each of the respective MBIST controllers, within the system, state clearing respective internal memories by writing pertinent MBIST data into the respective internal memories; and each of the respective EDT controllers, within the system, state clearing respective flip-flops by writing pertinent scan data into the respective flip-flops.
Facts
- Company
- Microsoft (Microsoft Technology Licensing, LLC)
- Official title
- State clearing of internal memory and flip-flops of a system using built-in test and scan circuitry
- Patent number
- US12730940B2
- Application number
- 18741536
- Filed
- Jun 12, 2024
- Granted
- Sep 8, 2026
- Inventors
- 3
- Claims
- 20
Classified under
G06F 21/78 Physics & computingG01R 31/318525 Physics & computingG01R 31/318597 Physics & computingG01R 31/3187 Physics & computingMore from Microsoft in Chips & hardware
- Microsoft patents chips with liquid cooling built inside Oct 1, 2026
- Microsoft patents chip design that guesses code steps ahead Sep 8, 2026
- Microsoft patents 3D glass storage using laser light patterns Sep 8, 2026
- Microsoft patents hand-held radar reflectors for tracking movement Sep 8, 2026
- Microsoft patents video boost that reuses old frames to save power Sep 15, 2026
Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.