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SonyPatent applicationChips & hardwareInterest 3/10

Sony patents chip package design with a barrier layer for easier cover removal

Patent drawing
Patent drawing from the official filing.

Sony has filed a patent for a semiconductor chip package that uses a specific metal barrier layer between the chip base and the top cover. This barrier prevents the solder used to hold the cover in place from mixing with other metals, which helps keep the connection stable during assembly. The design also allows the cover to be removed more easily if needed.

Why it mattersThis is a routine improvement in chip manufacturing that helps engineers build more reliable packages and potentially makes repairs or recycling easier.

In the filing’s own words

To improve stability at the time of mounting a cover while enabling removal of the cover of a package. The package includes: a cover; a mounting portion to which the cover is mounted; a barrier metal layer provided between the cover and the mounting portion; a metal bonding layer formed on the barrier metal layer; and a solder layer that is bonded to the metal bonding layer and connects the cover and the mounting portion. The barrier metal layer may not interdiffuse with the solder layer. The barrier metal layer may be formed on the cover. The barrier metal layer may be formed on the substrate. The barrier metal layer may be formed on the semiconductor chip.

What exactly they claim (claim 1)

1. A package comprising: a cover; a mounting portion to which the cover is mounted; a barrier metal layer provided between the cover and the mounting portion; a metal bonding layer formed on the barrier metal layer; and a solder layer that is bonded to the metal bonding layer and connects the cover and the mounting portion.

Facts

Company
Sony (SONY SEMICONDUCTOR SOLUTIONS CORPORATION)
Official title
PACKAGE AND METHOD FOR MANUFACTURING PACKAGE
Publication number
US20260333925A1
Application number
19122862
Filed
Aug 31, 2023
Published
Oct 22, 2026
Inventors
1
Claims
20

Classified under

H10F 39/811 Electricity & electronicsH10F 39/026 Electricity & electronicsH10F 39/804 Electricity & electronicsH10H 20/8506 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.