Sony patents camera sensor design that stacks chips to shrink pixels
Sony describes a camera sensor made by joining two separate silicon wafers face-to-face. This design places the light-capturing parts on one chip and the data-processing parts on the other, connected by tiny vertical wires that pass through the back chip.
In the filing’s own words
The present technology relates to a solid-state imaging device compatible with miniaturization of pixels, a method for manufacturing the solid-state imaging device, and an electronic apparatus. The solid-state imaging device is formed by joining a front surface side as the wiring layer formation surface of the first semiconductor substrate to a back surface side of the second semiconductor substrate. The first semiconductor substrate includes a photodiode and a transfer transistor. The second semiconductor substrate includes a charge/voltage retention portion that retains the electric charge transferred by the transfer transistor or the voltage corresponding to the electric charge. The solid-state imaging device includes a through electrode that penetrates the second semiconductor substrate, and transmits the electric charge or the voltage to the charge/voltage retention portion. The present technology can be applied to solid-state imaging devices and the like, for example.
What exactly they claim (claim 1)
1. A solid-state imaging apparatus, comprising: a first semiconductor substrate; a second semiconductor substrate, wherein a front surface side of the first semiconductor substrate forms a wiring layer formation surface of the first semiconductor substrate and joins to a back surface side of the second semiconductor substrate which is an opposite side of a wiring layer formation surface of the second semiconductor substrate, wherein the first semiconductor substrate includes: a photoelectric conversion portion that photoelectrically converts incident light; a transfer transistor that transfers electric charges of the photoelectric conversion portion; and a voltage conversion transistor that converts the electric charges transferred by the transfer transistor into a corresponding voltage, and wherein the second semiconductor substrate includes a charge voltage retention portion that retains the corresponding voltage converted by the voltage conversion transistor; and a through electrode that penetrates through the second semiconductor substrate and transmits the corresponding voltage converted by the transfer transistor to the charge voltage retention portion, wherein the transfer transistor and the voltage conversion transistor are formed on a surface of the second semiconductor substrate, opposite a light incident side of the first semiconductor substrate and wherein the through electrode does not penetrate through the first semiconductor substrate.
Facts
- Company
- Sony (SONY SEMICONDUCTOR SOLUTIONS CORPORATION)
- Official title
- Solid-state imaging device, method for manufacturing the same, and electronic apparatus
- Patent number
- US12733287B2
- Application number
- 18491450
- Filed
- Oct 20, 2023
- Granted
- Sep 8, 2026
- Inventors
- 1
- Claims
- 20
Classified under
H10F 39/811 Electricity & electronicsH04N 25/67 Electricity & electronicsH04N 25/70 Electricity & electronicsH04N 25/77 Electricity & electronicsH04N 25/79 Electricity & electronicsH10F 39/018 Electricity & electronicsMore from Sony in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.