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Nvidia patents method to check if different sorting chips produce same results

Patent drawing
Patent drawing from the official filing.

Nvidia describes a system for verifying that two different hardware designs for sorting data produce identical outputs. Instead of checking every internal step, the method uses mathematical rules to define what correct sorted output looks like and compares the final results of both designs.

Why it mattersThis technique helps engineers ensure that complex sorting circuits work correctly without needing to map every internal connection, potentially speeding up the design process for computer chips.

In the filing’s own words

Apparatuses, systems, and techniques for formal verification of computational agents using output specification constraints are disclosed herein, for example in the context of formal verification of sorting hardware components using property-based abstraction methodologies. A hardware verification system can define abstraction properties that uniquely characterize outputs of sorting algorithms and prove equivalence between algorithmically distinct sorting implementations using a formal equivalence checking tool. Constraint application nodes can introduce symbolic placeholder variables at sorting outputs, where the symbolic variables are constrained by the abstraction properties, enabling equivalence verification without requiring internal equivalence points between implementations and improving convergence behavior of formal verification tools.

What exactly they claim (claim 1)

1. A hardware verification system comprising: one or more processors to: obtain a set of output specification constraints that collectively characterizes outputs of sorting agents and comprises at least an ordering constraint specifying sorted order of the outputs; and verify output correspondence between a first sorting agent and a second sorting agent within a formal equivalence checking tool by introducing constraint application nodes at outputs of the first sorting agent, wherein the constraint application nodes comprise placeholder variables that replace signal values of the outputs of the first sorting agent during hardware verification, and wherein the placeholder variables are subject to the set of output specification constraints.

Facts

Company
Nvidia (NVIDIA Corporation)
Official title
FORMAL VERIFICATION OF COMPUTATIONAL AGENTS USING OUTPUT SPECIFICATION CONSTRAINTS
Publication number
US20260330116A1
Application number
19576743
Filed
Mar 24, 2026
Published
Oct 22, 2026
Inventors
1
Claims
20

Classified under

G06F 30/3323 Physics & computingG06F 30/327 Physics & computing

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.