Sony patents chip design that cuts unwanted electrical noise
Sony describes a semiconductor structure that places a specific gap between the chip's main body and the wiring on its back side. This setup uses distinct layers of material to reduce parasitic capacitance, which is an unwanted electrical effect that can slow down signals.
In the filing’s own words
A parasitic capacitance of a wiring arranged on a back surface side of a semiconductor substrate is reduced. A semiconductor apparatus includes a semiconductor substrate, a back surface side wiring, a through wiring, and a separation region. In the semiconductor substrate, a semiconductor element and a front surface side wiring connected to the semiconductor element are arranged on a front surface side. The back surface side wiring is arranged on a back surface side of the semiconductor substrate. The through wiring is arranged in a through hole formed in the semiconductor substrate to connect the front surface side wiring and the back surface side wiring. The separation region is arranged between the semiconductor substrate and the back surface side wiring.
What exactly they claim (claim 1)
1. A semiconductor apparatus, comprising: a semiconductor substrate in which a semiconductor element and a front surface side wiring connected to the semiconductor element are on a front surface side; a back surface side wiring on a back surface side of the semiconductor substrate; a separation region between the semiconductor substrate and the back surface side wiring, wherein the separation region includes a layer of material disposed on the back surface side of the semiconductor substrate; and an insulating film between the separation region and the back surface side wiring, wherein the insulating film and the separation region are distinct layers, and wherein a material composition of the insulating film is different than a material composition of the separation region.
Facts
- Company
- Sony (SONY SEMICONDUCTOR SOLUTIONS CORPORATION)
- Official title
- SEMICONDUCTOR APPARATUS AND METHOD FOR MANUFACTURING SEMICONDUCTOR APPARATUS
- Publication number
- US20260324120A1
- Application number
- 19718314
- Filed
- Jun 24, 2026
- Published
- Oct 15, 2026
- Inventors
- 6
- Claims
- 20
Classified under
H10F 39/811 Electricity & electronicsH10W 20/023 Electricity & electronicsH10W 20/20 Electricity & electronicsMore from Sony in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.