Samsung patents memory trick to run AI tasks in chunks
Samsung describes a method for running artificial intelligence models by breaking them into smaller parts called segments. A hardware component loads these segments into memory one at a time, allowing the processor to work on one part while the next part is being loaded.
In the filing’s own words
A computing device includes a memory device, a direct memory access (DMA) controller that is configured to load a first task into the memory device on a segment-by-segment basis, the first task being associated with a deep neural network (DNN) model and including a plurality of segments, and wherein the plurality of segments include a first segment and a second segment; and a processor configured to execute at least one segment loaded in the memory device on a segment-by-segment basis, wherein each of the plurality of segments is included in one of a plurality of segment groups, the plurality of segment groups including a first segment group and a second segment group.
What exactly they claim (claim 1)
1. A computing device comprising: a memory device; a direct memory access (DMA) controller that is configured to load a first task into the memory device on a segment-by-segment basis, the first task being associated with a deep neural network (DNN) model and comprising a plurality of segments, and wherein the plurality of segments comprise a first segment and a second segment; and a processor configured to execute at least one segment loaded in the memory device on a segment-by-segment basis, wherein each of the plurality of segments is comprised in one of a plurality of segment groups, the plurality of segment groups comprising a first segment group and a second segment group, wherein the memory device comprises a first memory area and a second memory area, and the first memory area and the second memory area are separately allocated in the memory device, wherein the DMA controller is further configured to, during a time that data associated with the first segment comprised in the first segment group is maintained in the first memory area, load data associated with the second segment included in the second segment group into the second memory area, and wherein the processor is further configured to access the first memory area during a same time the DMA controller accesses the second memory area.
Facts
- Company
- Samsung (SAMSUNG ELECTRONICS CO., LTD.)
- Official title
- MEMORY MANAGEMENT AND TASK SCHEDULING IN COMPUTING DEVICES AND COMPUTING SYSTEMS
- Publication number
- US20260319980A1
- Application number
- 19368750
- Filed
- Oct 24, 2025
- Published
- Oct 15, 2026
- Inventors
- 3
- Claims
- 20
Classified under
G06F 13/28 Physics & computingMore from Samsung in AI & software
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.