NvidiaPatent applicationChips & hardwareInterest 6/10

Nvidia patents chip trick to speed up math with block scaling

Patent drawing from the official filing.

Nvidia describes a method for processors to perform matrix multiply-accumulate operations, which are core calculations for running complex software. The technique involves multiplying parts of a data matrix by specific scale factors stored in memory before the main calculation happens.

Why it mattersThis filing details a specific way to handle data in Nvidia's chips, which could make their hardware more efficient for tasks like running large software models.

In the filing’s own words

Apparatuses, systems, and techniques to perform matrix multiply-acumulate operations with block scaling of specified portions of input matrices by scale factors. In at least one embodiment, an input matrix is multiplied by a scaled matrix that is generated by multiplying elements of a second input matrix by one or more corresponding scale factors stored in tensor memory.

What exactly they claim (claim 1)

1. One or more processors, comprising: circuitry to perform an instruction to perform one or more matrix multiply-accumulate (MMA) operations to multiply a first input matrix by a scaled matrix generated by multiplying one or more elements of a second input matrix by one or more corresponding scale factors stored in tensor memory.

Facts

Company: Nvidia (NVIDIA Corporation)
Official title: MATRIX MULTIPLICATION WITH BLOCK SCALING
Publication number: US20260310750A1
Application number: 19317089
Filed: Sep 2, 2025
Published: Oct 8, 2026
Inventors: 4
Claims: 20

Classified under

G06F 17/16 Physics & computing

Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.