Nvidia patents grid layout for testing stacked chip connections
Nvidia describes a design for stacked semiconductor chips that includes a grid of small test areas on the surface. These areas contain specific pads that allow engineers to check electrical connections between the stacked layers.
In the filing’s own words
In accordance with the disclosure, an inductor may be formed over a semiconductor substrate of one or both dies in a face-to-face die arrangement while reducing the parasitic capacitance between the inductor and the adjacent die. In disclosed embodiments, a semiconductor device may include a void (e.g., an air gap) between the inductor and the adjacent die to reduce the parasitic capacitance between the inductor and the adjacent die. The void may be formed in the die that includes the inductor and/or the adjacent die. In some respects, the void may be etched in interface layers (e.g., comprising bump pads and dielectric material) between the semiconductor dies, and may extend along the length of the inductor.
What exactly they claim (claim 1)
1. A semiconductor device comprising: testing tile structures disposed on a face of a semiconductor die and arranged in a grid, the testing tile structures each including one or more probe pads; and a crossbar situated between at least two of the testing tile structures within the grid and configured to communicate signals between the semiconductor die and at least one other semiconductor die.
Facts
- Company
- Nvidia (NVIDIA Corporation)
- Official title
- TESTING TILE STRUCTURES
- Publication number
- US20260293717A1
- Application number
- 19694655
- Filed
- Jun 1, 2026
- Published
- Sep 24, 2026
- Inventors
- 2
- Claims
- 20
Classified under
H10W 70/611 Electricity & electronicsH10D 1/20 Electricity & electronicsH10W 20/20 Electricity & electronicsH10W 70/635 Electricity & electronicsH10W 72/20 Electricity & electronicsH10W 90/00 Electricity & electronicsMore from Nvidia in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.