Nvidia patents AI tool to predict chip layout congestion
Nvidia describes a method for designing computer chips that uses a machine learning model to predict where components might crowd together. The system analyzes the initial layout of chip cells, converts it into a graph, and uses the prediction to adjust where those cells are placed to avoid overcrowding.
In the filing’s own words
Apparatuses, systems, and techniques for bounding area planning using a congestion prediction model. Placement data associated with cells of an IC design is identified. A graph based at least on the identified placement data is generated. The graph is provided as input to a machine learning model. The machine learning model is trained to predict, based at least on a given graph associated with cells according to a respective IC design, a congestion level for cells at one or more bounding areas of a respective IC design. One or more outputs of the machine learning model are obtained. The one or more outputs include congestion data indicating a congestion level for a first bounding area of the IC design. Cells are caused to be placed within at least one region, of the IC design, corresponding to the first bounding area.
What exactly they claim (claim 1)
1. A method comprising: identifying placement data associated with a plurality of cells of an integrated circuit (IC) design, wherein the placement data indicates an initial placement location for at least a subset of the plurality of cells of the IC design; generating a graph based at least on the identified placement data, wherein one or more nodes of the graph correspond to a respective cell of the plurality of cells; providing the graph as input to a machine learning model, wherein the machine learning model is trained to predict, based at least on a given graph associated with cells according to a respective IC design, a congestion level for cells at one or more bounding areas of the respective IC design; obtaining one or more outputs of the machine learning model, wherein the one or more outputs comprise congestion data indicating a congestion level for a first bounding area of the IC design; and causing placement of the plurality of cells within at least one region, of the IC design, corresponding to the first bounding area based on the congestion data.
Facts
- Company
- Nvidia (NVIDIA Corporation)
- Official title
- BOUNDING AREA PLANNING USING A CONGESTION PREDICTION MODEL
- Publication number
- US20260289339A1
- Application number
- 19684992
- Filed
- May 21, 2026
- Published
- Sep 24, 2026
- Inventors
- 2
- Claims
- 22
Classified under
G06N 5/022 Physics & computingMore from Nvidia in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.