Nvidia patents GPU design that keeps data on local chips to speed up graphics
Nvidia describes a method for multi-chip graphics processors where each chip stores specific rendering data in its own local memory instead of sharing it across chips. This approach reduces the amount of data that needs to travel between the separate chips, which can lower latency and improve overall performance.
In the filing’s own words
Methods and systems are described for localizing writes of certain graphics pipeline attributes, localizing certain page pool and root table version buffers, and/or localizing of local memory in order to improve the latency of write operations and/or to reduce the inter-chip traffic in a multi-chip graphics processing unit (GPU) that uses a common unified memory. The described localizing may be implemented over a coarse-grained interleaving of the virtual memory on the locally connected memories of each GPU in the multi-chip GPU.
What exactly they claim (claim 1)
1. In a multi-chip GPU including first rendering hardware disposed on a first die for rendering first pixels into a first frame buffer tile and second rendering hardware disposed on a second die for rendering second pixels into a second frame buffer tile, the first die and the second die communicating via a chip-to-chip communication interface, a method comprising: (a) the first rendering hardware writing first rendering parameters to first point of coherence memory locally connected to the first die without requiring writes over the chip-to-chip communication interface to the second die, and (b) the second rendering hardware writing second rendering parameters to second point of coherence memory locally connected to the second die without requiring writes over the chip-to-chip communication interface to the first die, wherein the first rendering hardware and the second rendering hardware are each configured to locally cache portions of the first rendering parameters written to the first point of coherence memory locally connected to the first die and the second rendering parameters written to the second point of coherence memory locally connected to the second die.
Facts
- Company
- Nvidia (NVIDIA Corporation)
- Official title
- LOCALIZATION OF VERTEX ATTRIBUTES, CONSTANTS AND LOCAL MEMORY IN A MULTI-CHIP GPU
- Publication number
- US20260288335A1
- Application number
- 19087436
- Filed
- Mar 21, 2025
- Published
- Sep 24, 2026
- Inventors
- 4
- Claims
- 24
Classified under
G06F 3/0611 Physics & computingG06F 3/0656 Physics & computingG06F 3/0659 Physics & computingG06F 3/0673 Physics & computingG06F 12/0815 Physics & computingMore from Nvidia in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.