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SonyPatent applicationChips & hardwareInterest 2/10

Sony patents chip design that routes wires at specific angles

Sony describes a semiconductor device where a chip sits on top of a wiring layer. The filing specifies that signal lines on this layer must cross the chip's boundary at an angle smaller than a set limit to improve reliability.

Why it mattersThis is a technical adjustment to how wires are laid out under a chip, which helps ensure the device works consistently without failing.

In the filing’s own words

Reliability is improved in a semiconductor device in which a semiconductor chip is stacked on a wiring layer. The semiconductor device includes a wiring layer, a semiconductor chip stacked in a predetermined region on a wiring surface of the wiring layer, and a signal line that is wired on the wiring surface and has an angle less than a predetermined angle in at least one of two regions divided by any boundary line of the predetermined region, the angle being formed when the signal line crosses the boundary line. The semiconductor chip is stacked in a predetermined region on the wiring surface of the wiring layer. The signal line is wired on the wiring surface and has an angle less than the predetermined angle in at least one of two regions divided by any boundary line of the predetermined region, the angle being formed when the signal line crosses the boundary line.

What exactly they claim (claim 1)

1. A semiconductor device comprising: a wiring layer; a semiconductor chip stacked in a predetermined region on a wiring surface of the wiring layer; and a signal line that is wired on the wiring surface and has an angle less than a predetermined angle in at least one of two regions divided by any boundary line of the predetermined region, the angle being formed when the signal line crosses the boundary line.

Facts

Company
Sony (SONY GROUP CORPORATION)
Official title
SEMICONDUCTOR DEVICE
Publication number
US20260282973A1
Application number
19673721
Filed
May 11, 2026
Published
Sep 17, 2026
Inventors
2
Claims
17

Classified under

H10W 70/65 Electricity & electronicsH10W 70/685 Electricity & electronicsH10W 90/00 Electricity & electronicsH10W 70/60 Electricity & electronicsH10W 72/0198 Electricity & electronicsH10W 72/877 Electricity & electronics
Read the full filing (official PDF) ↗ Open in the Patent Tracker

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.