Nvidia patents method to split large data chunks for faster chip processing
Nvidia describes a technique where a software compiler breaks large blocks of data, called tiles, into smaller pieces known as sub-tiles. The system sizes these pieces based on the specific hardware capabilities of the processor and arranges the instructions in a specific order to run them efficiently.
In the filing’s own words
Processors, systems, and techniques to cause a compiler to partition a tile of a tile program into a plurality of sub-tiles and perform tile program operations on the sub-tiles in a determined order. In at least one embodiment a compiler is to partition a tile of a tile program into a plurality of sub-tiles, wherein the compiler determines a size of the sub-tiles based, at least in part, on one or more accelerator hardware characteristics. The compiler is further to generate a plurality of instruction groups to be performed on corresponding sub-tiles of the plurality of sub-tiles, wherein the instruction groups are based, at least in part, on a tile operation to be performed on the tile of the tile program, determine an order to perform individual instruction groups of the plurality of instruction groups, and generate code to cause individual instruction groups to be performed in the determined order.
What exactly they claim (claim 1)
1. One or more processors, comprising: circuitry to cause a compiler to: partition a tile of a tile program into a plurality of sub-tiles, wherein the compiler determines a size of the sub-tiles based, at least in part, on one or more accelerator hardware characteristics; generate a plurality of instruction groups to be performed on corresponding sub-tiles of the plurality of sub-tiles, wherein the instruction groups are based, at least in part, on a tile operation to be performed on the tile of the tile program; determine an order to perform individual instruction groups of the plurality of instruction groups; and generate code to cause individual instruction groups to be performed in the determined order.
Facts
- Company
- Nvidia (NVIDIA Corporation)
- Official title
- TILE PROGRAM OPTIMIZATION USING SUB-TILES
- Publication number
- US20260277569A1
- Application number
- 19530265
- Filed
- Feb 4, 2026
- Published
- Sep 17, 2026
- Inventors
- 5
- Claims
- 20
Classified under
G06F 8/41 Physics & computingMore from Nvidia in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.