Nvidia patents chip feature that calculates stats while moving data
Nvidia describes a hardware design for graphics processors that calculates basic statistics, like the highest or lowest number, while data is being moved between memory units. This happens in one step, so the computer does not need to pause and run a separate calculation after the data arrives.
In the filing’s own words
Apparatuses, systems, and techniques for performing statistical calculations during data transport in graphics processing units are disclosed herein. The system may include a statistical reduction circuit coupled to a data transport circuit. The statistical reduction circuit performs statistical reduction operations on data elements during transfer from tensor memory or directly from matrix multiply-accumulate arrays to register files. The statistical reduction circuit may compute running statistical values as each data element is transferred, eliminating separate computational passes. The system may include not-a-number handling circuitry that implements filtering modes for wide reduction operations. The system may support statistical operations such as determination of a maximum value, a minimum value, and absolute value variants, while processing multiple numeric formats. The integrated statistical computation capability can reduce latencies and eliminate register file bandwidth conflicts during statistical processing through concurrent data movement and statistical computation.
What exactly they claim (claim 1)
1. A processing device comprising: a tensor memory to store matrix multiply-accumulate operation results; a register file to store data for arithmetic operations; a data transport circuit coupled to at least one of the tensor memory or matrix multiply-accumulate arrays, and coupled to the register file, the data transport circuit to transfer data elements from at least one of the tensor memory or the matrix multiply-accumulate arrays to the register file; a statistical reduction circuit coupled to the data transport circuit, the statistical reduction circuit to perform a statistical reduction operation on the data elements during the transfer of the data elements from the at least one of the tensor memory or the matrix multiply-accumulate arrays to the register file; and a control circuit to execute a single instruction that causes both the transfer of the data elements and the statistical reduction operation to occur concurrently.
Facts
- Company
- Nvidia (NVIDIA Corporation)
- Official title
- HARDWARE CIRCUIT FOR STATISTICAL REDUCTION DURING DATA TRANSPORT
- Publication number
- US20260277545A1
- Application number
- 19445070
- Filed
- Jan 9, 2026
- Published
- Sep 17, 2026
- Inventors
- 5
- Claims
- 20
Classified under
G06F 7/523 Physics & computingG06F 7/50 Physics & computingMore from Nvidia in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.