Sony patents stacked chip design to fit more transistors in less space

1. A semiconductor device, comprising: a conductive substrate; an insulating material layer, wherein a first surface of the insulating material layer is in contact with and is disposed on a surface of the conductive substrate; a plurality of gate electrode layers, wherein each gate electrode layer in the plurality of gate electrode layers is disposed on a second surface of the insulating material layer, and wherein the second surface of the insulating material layer is opposite the first surface of the insulating material layer; a plurality of channel formation region layers, wherein each channel formation region layer in the plurality of channel formation region layers is disposed on the second surface of the insulating material layer, wherein each channel formation region layer in the plurality of channel formation region layers is disposed between a unique pair of gate electrode layers of the plurality of gate electrode layers; a first source/drain region, wherein the first source/drain region is disposed on the second surface of the insulating material layer, wherein the first source/drain region is in contact with a first side surface of each of the channel formation region layers in the plurality of channel formation region layers; a second source/drain region, wherein the second source/drain region is disposed on the second surface of the insulation material layer, wherein the second source/drain region is in contact with a second side surface of each of the channel formation region layers in the plurality of channel formation region layers, and wherein the first side surface of the channel formation region layers is opposite the second side surface of the channel formation region layers; a first insulating film, wherein the first insulating film is disposed on first side surfaces of each of the gate electrode layers in the plurality of gate electrode layers, and wherein the first insulating film lies between the first side surfaces of each of the gate electrode layers in the plurality of gate electrode layers and the first source/drain region; and a second insulating film, wherein the second insulating film is disposed on second side surfaces of each of the gate electrode layers in the plurality of gate electrode layers, wherein the second insulating film lies between the second side surfaces of each of the gate electrode layers in the plurality of gate electrode layers and the second source/drain region, wherein a bottom surface of each gate electrode layer in the plurality of gate electrode layers is in direct contact with the insulating material layer, wherein the first insulating film and the second insulating film include are formed from an insulating portion, and wherein the insulating portion is in direct contact with first, second, third, and fourth side surfaces of at least one gate electrode layer in the plurality of gate electrode layers.