Nvidia patents faster memory setup by tracking specific error patterns
Nvidia describes a method for computers to tune their connection to memory chips more quickly. Instead of checking every possible signal shape, the system sends known data patterns and counts errors only for those specific patterns. It then uses these counts to calculate the correct settings for cleaning up the signal.
In the filing’s own words
A system includes a memory device and one or more processing devices operatively coupled to the memory device via a memory channel. The processing device(s) cause data to be received over the memory channel from the memory device, where the data includes known multi-bit patterns. The processing device(s) sweep the data over voltage and time to generate eye diagram data. The processing device(s) detect errors at identified cursors of the eye diagram data, where each identified cursor corresponds to a known multi-bit pattern within a set of previously transmitted bits. The processing device(s) store counts of each detected error associated with a respective known multi-bit pattern. The processing device(s) determine, using the counts, a plurality of decision feedback equalizer (DFE) coefficients to be employed in receiving unknown data over the memory channel.
What exactly they claim (claim 1)
1. A system comprising: a memory device; and one or more processing devices operatively coupled to the memory device via a memory channel, wherein the one or more processing devices are to: cause data to be received over the memory channel from the memory device, wherein the data comprises known multi-bit patterns; sweep the data over voltage and time to generate eye diagram data, wherein, to sweep the data, the one or more processing devices are to: turn off equalization of the memory channel; and sweep across voltage and phase dimensions of the data for each known multi-bit pattern; detect errors at identified cursors of the eye diagram data, wherein each identified cursor corresponds to a known multi-bit pattern within a set of previously transmitted bits; store counts of each detected error associated with a respective known multi-bit pattern of the set of previously transmitted bits; and determine, using the counts, a plurality of decision feedback equalizer (DFE) coefficients to be employed in receiving unknown data over the memory channel.
Facts
- Company
- Nvidia (NVIDIA Corporation)
- Official title
- Priori bit pattern indexed error counts for accelerated link equalization training
- Patent number
- US12771475B2
- Application number
- 18972382
- Filed
- Dec 6, 2024
- Granted
- Oct 20, 2026
- Inventors
- 2
- Claims
- 20
Classified under
H04L 1/0054 Electricity & electronicsH03M 13/2957 Electricity & electronicsH03M 13/3905 Electricity & electronicsMore from Nvidia in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.