Nvidia patents chip layout method to reduce clock signal errors
Nvidia describes a method for arranging specific components, called flip-flops, on a computer chip to improve how the clock signal travels. The system groups these components based on their timing needs and places them in diamond-shaped patterns. This layout helps create a more regular clock tree, which reduces variations in the signal and improves overall chip performance.
In the filing’s own words
Mechanisms to place flip-flops and other synchronous logic cells in a circuit layout in a clock on-chip variation-aware, predetermined order based on analysis of the clock gating, connectivity, and logic depth of the unplaced netlist. The resulting placements enable clock trees having a regular structure leading to improvements in clock on-chip variation, timing, and clock power.
What exactly they claim (claim 1)
1. A method of generating a clock tree for a circuit, the method comprising: clustering synchronous logic cells of the circuit according to their interactive timing behavior; placing resulting clusters of the synchronous logic cells in the circuit in cells of diamond-shaped patches; and generating the clock tree as traces from centers of the patches to the cells.
Facts
- Company
- Nvidia (NVIDIA Corp.)
- Official title
- Logic cell placement mechanisms for improved clock on-chip variation
- Patent number
- US12769924B2
- Application number
- 18178375
- Filed
- Mar 3, 2023
- Granted
- Oct 20, 2026
- Inventors
- 3
- Claims
- 20
Classified under
G06F 30/396 Physics & computingG06F 30/392 Physics & computingG06F 2119/12 Physics & computingMore from Nvidia in Chips & hardware
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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.