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Sony patents semiconductor resistor design to cut unwanted electrical noise

Sony has been granted a patent for a specific way to build resistors inside chips. The design uses two layers of material with different electrical properties to reduce stray electrical connections, known as parasitic capacitance, between the top and bottom contacts.

Why it mattersThis is a routine improvement in chip manufacturing that helps engineers build more precise electronic components, though it does not describe a new consumer product.

In the filing’s own words

To provide a semiconductor device with which it is possible to reduce parasitic capacitance between electrodes for a resistance element, and a method for manufacturing the semiconductor device. A semiconductor device according to the present disclosure includes: a substrate; a first resistance layer provided on the substrate; a first electrode in contact with a lower surface of the first resistance layer; and a second electrode in contact with an upper surface of the first resistance layer.

What exactly they claim (claim 1)

1. A semiconductor device, comprising: a substrate; a first resistance layer provided on the substrate; a first electrode in contact with a lower surface of the first resistance layer; and a second electrode in contact with an upper surface of the first resistance layer, wherein the first resistance layer includes a first layer and a second layer having an electrical resistivity lower than an electrical resistivity of the first layer, wherein the second layer includes a first portion having a bottom surface that is connected with the first electrode and a second portion having a top surface that is coupled with the second electrode via the first resistance layer, wherein the second portion is separated from the first portion and a bottom surface of the second portion is free of electrical connection.

Facts

Company
Sony (SONY SEMICONDUCTOR SOLUTIONS CORPORATION)
Official title
Semiconductor device with resistor and method for manufacturing same
Patent number
US12765104B2
Application number
18001767
Filed
Apr 6, 2021
Granted
Oct 13, 2026
Inventors
4
Claims
19

Classified under

H10F 39/811 Electricity & electronicsH10D 1/47 Electricity & electronicsH10D 1/474 Electricity & electronicsH10F 30/225 Electricity & electronicsH10F 39/011 Electricity & electronicsH10W 20/498 Electricity & electronics

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Summaries are simplified from the filing’s own abstract and first claim. A patent filing is not a product announcement.
Patent data and drawings: U.S. Patent and Trademark Office (USPTO). Nebula is not affiliated with or endorsed by the USPTO.